AN ULTRA-HIGH-SPEED ECL-BICMOS TECHNOLOGY WITH SILICON FILLET SELF-ALIGNED CONTACTS

Abstract

We have developed a half-micron super self-aligned BiCMOS technology for high speed application. A new Silicon Fillet self-aligned conTact (SIFT) process is integrated in this BiCMOS technology enabling high speed performances for both CMOS and ECL bipolar circuits. In this paper, we describe the process design, device characteristics and circuit performance of this BiCMOS technology. The minimum CMOS gate delay is 38 ps on 0.5 mum gate and 50 ps on 0.6 mum gate ring oscillators at 5 V. Bipolar ECL gate delay is 24 ps on 0.6 mum emitter ring oscillators with collector current density of 40 kA/cm2. A single phase decision circuit operating error free over 8 Gb/s and a static frequency divider operating at 13.5 GHz is demonstrated in our BiCMOS technology.