A systolic realization of symmetric block matching algorithm for HD-MAC system

Abstract

This paper describes a method for VLSI realization of symmetric block matching algorithm(SBMA) with systolic array processors. The VLSI implementation of SBMA has some problems, because the blocks in the current frame are matched to the averaged blocks of the corresponding previous and next frames. In order to solve such problems, we propose a new error measure with some merits in the aspect of real motion as well as VLSI implementation. We, also, present a VLSI architecture for SBMA with the proposed measure.