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NEW HARDWARE-BASED CLOCK SYNCHRONIZATION FOR THE BYZANTINE FAULT

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dc.contributor.authorBAEK, YJko
dc.contributor.authorLEE, HKko
dc.contributor.authorYoon, Hyunsooko
dc.date.accessioned2013-02-25T21:46:53Z-
dc.date.available2013-02-25T21:46:53Z-
dc.date.created2012-02-06-
dc.date.created2012-02-06-
dc.date.issued1992-10-
dc.identifier.citationELECTRONICS LETTERS, v.28, no.21, pp.2018 - 2019-
dc.identifier.issn0013-5194-
dc.identifier.urihttp://hdl.handle.net/10203/65542-
dc.description.abstractA new approach for fault-tolerant clock synchronisation which uses digital clocks instead of the conventional PLLs (phase-locked loops) is presented. In this circuit the delay time of the clock system is much reduced and the exact maximum clock skew is obtained to guarantee the tightness of the synchronisation.-
dc.languageEnglish-
dc.publisherIEE-INST ELEC ENG-
dc.titleNEW HARDWARE-BASED CLOCK SYNCHRONIZATION FOR THE BYZANTINE FAULT-
dc.typeArticle-
dc.identifier.wosidA1992JU18900050-
dc.identifier.scopusid2-s2.0-0027115394-
dc.type.rimsART-
dc.citation.volume28-
dc.citation.issue21-
dc.citation.beginningpage2018-
dc.citation.endingpage2019-
dc.citation.publicationnameELECTRONICS LETTERS-
dc.contributor.localauthorYoon, Hyunsoo-
dc.contributor.nonIdAuthorBAEK, YJ-
dc.contributor.nonIdAuthorLEE, HK-
dc.type.journalArticleArticle-
dc.subject.keywordAuthorCOMPUTER METATHEORY-
dc.subject.keywordAuthorHARDWARE FAULT TOLERANT CLOCK SYNCHRONIZATION-
dc.subject.keywordAuthorBYZANTINE FAULT-
dc.subject.keywordAuthorINTERACTIVE CONVERGENCE ALGORITHM-
dc.subject.keywordPlusSYNCHRONIZATION-
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CS-Journal Papers(저널논문)
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