DC Field | Value | Language |
---|---|---|
dc.contributor.author | Ryu W. | ko |
dc.contributor.author | Wai A.L.C. | ko |
dc.contributor.author | Wei F. | ko |
dc.contributor.author | Lai W.L. | ko |
dc.contributor.author | Kim, Joungho | ko |
dc.date.accessioned | 2007-06-26T03:05:35Z | - |
dc.date.available | 2007-06-26T03:05:35Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2002-02 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON ADVANCED PACKAGING, v.25, no.1, pp.18 - 27 | - |
dc.identifier.issn | 1521-3323 | - |
dc.identifier.uri | http://hdl.handle.net/10203/653 | - |
dc.description.abstract | Conventional interconnections for digital clock distribution pose a severe power consumption problem for GHz clock distribution, because of transmission line losses. They also pose difficult signal integrity problems because of clock skew, clock jitter, and signal reflection. To overcome these conventional digital clock distribution limitations, optical clock distribution techniques, based on guided-wave optics and free-space optics, have been proposed. However, optical clock distribution is bulky, difficult to fabricate, and expensive, even though it has lower power consumption and excellent signal integrity properties. Therefore, we have proposed a RF clock distribution (RCD) scheme for high-speed digital applications, in particular a multiprocessor system using global clocking. This paper first reports system power and signal integrity analysis results including skew, jitter, impedance mismatch, and noise for RF clock distribution, especially in the GHz range. Based on this analysis, a novel signal integrity design methodology for RF clock distribution systems is proposed. The clock skew created by process parameter variations are modeled and predicted. The system comprises a RF clock transmitter as a clock generator, an H-tree with junction couplers as a clock distributing network and a RF receiver as a digital clock-recovery module. Flip-chip interconnections for the chip-to-substrate assembly and 0.35 mum TSMC CMOS technology for the RF clock receiver are assumed. EMI analysis for 2 GHz 16-node board-level RF clock distribution networks is conducted using 3-D full-wave electromagnetic (EM) simulation. Finally, the RCD as a low power and high performance clocking method is demonstrated using HP's Advanced Design System (ADS) simulation, considering microwave frequency interconnection models and process parameter variations. In addition, test vehicles for both 2 GHz 16-node and 5 GHz 64-node board-level RF clock distribution networks were implemented and measured using thin, low-loss, and low permittivity Rogers(R) RO3003 high-frequency organic substrate. | - |
dc.description.sponsorship | The authors would like to thank L. C. Lee, C. K. Wong, Z. Wang, Gintic Institute of Manufacturing Technology, and C. L. Law, Nanyang Technology University, for their support for this work, L. K. Cheah and Dr. Mohaime, Gintic Institute of Manufacturing Technology, for their assistance in fabricating PCB, and C. K. Cheng, Gintic Institute of Manufacturing Technology, for his assistance in PCB assembly. | en |
dc.language | English | - |
dc.language.iso | en_US | en |
dc.publisher | Institute of Electrical and Electronics Engineers | - |
dc.subject | INTERCONNECTIONS | - |
dc.title | Over GHz low-power RF clock distribution for a multiprocessor digital system | - |
dc.type | Article | - |
dc.identifier.wosid | 000176858600004 | - |
dc.identifier.scopusid | 2-s2.0-0036478884 | - |
dc.type.rims | ART | - |
dc.citation.volume | 25 | - |
dc.citation.issue | 1 | - |
dc.citation.beginningpage | 18 | - |
dc.citation.endingpage | 27 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON ADVANCED PACKAGING | - |
dc.embargo.liftdate | 9999-12-31 | - |
dc.embargo.terms | 9999-12-31 | - |
dc.contributor.localauthor | Kim, Joungho | - |
dc.contributor.nonIdAuthor | Ryu W. | - |
dc.contributor.nonIdAuthor | Wai A.L.C. | - |
dc.contributor.nonIdAuthor | Wei F. | - |
dc.contributor.nonIdAuthor | Lai W.L. | - |
dc.type.journalArticle | Article; Proceedings Paper | - |
dc.subject.keywordAuthor | board-level clock distribution | - |
dc.subject.keywordAuthor | GHz and low power clock distribution | - |
dc.subject.keywordAuthor | multiprocessor computer system | - |
dc.subject.keywordAuthor | radio-frequency (RF) clock distribution | - |
dc.subject.keywordAuthor | system signal integrity | - |
dc.subject.keywordPlus | INTERCONNECTIONS | - |
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