EXTRINSIC VERSUS INTRINSIC MODELS FOR FETS

Abstract

The importance of a proper inclusion of parasitic source and drain resistances in various FET device models used in circuit simulation with SPICE is pointed out. Although a significant reduction in simulation time can be achieved using so-called extrinsic FET models, some problems are encountered in cases where gate leakage current is present and in simulating transients. Moreover, an intrinsic model with parasitics is more compatible with high frequency small signal equivalent circuits.