A study of pipeline architectures for high-speed synchronous DRAMs

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The performances of SDRAM's with different pipeline architectures are examined analytically on the basis of the time required to refill the on-chip cache of a Pentium CPU. The analysis shows that the cycle time of the conventional pipeline structures cannot be reduced because of its difficulty in distributing the access time evenly to each pipeline stage of the column address access path. On the contrary, the wave pipeline architecture can make the access path evenly divided and can increase the number of pipeline stages to achieve the shortest cache refill time. But the wave congestion at the output terminal of the wave pipeline path caused by access time fluctuation narrows the valid time window. The parallel registered wave pipeline architecture can remove the effect of access time fluctuation so that the cycle time is defined only by the data pulse width. If the data pulse width t(w) < 2 ns, even 500-MHz clock frequency can be obtained.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
1997-10
Language
English
Article Type
Article
Citation

IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.32, no.10, pp.1597 - 1603

ISSN
0018-9200
URI
http://hdl.handle.net/10203/6324
Appears in Collection
EE-Journal Papers(저널논문)
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