A 0.7-fJ/bit/search 2.2-ns search time hybrid-type TCAM architecture

Abstract

This paper presents a hybrid-type TCAM architecture which can utilize the benefits of both NOR and NAND-type TCAM cells: high speed and low power. A hidden bank selection scheme is proposed to activate limited amount of cells during the search operation avoiding additional timing penalty. Match line repeaters and sub-match line scheme are used for fast NAND search operation. A test chip with 144-kb TCAM capacity is implemented using 0.1-mum 1.2-V CMOS process to verify the proposed schemes. It shows 2.2 ns of match evaluation time on a 144-bit data search with 0.7 fJ/bitt/search energy efficiency.