A 0.9 V 96 mu W fully operational digital hearing aid chip

Abstract

A 0.9 V 96 mu W fully operational low-power digital hearing aid chip is proposed and implemented. An internal status controller is introduced to achieve full operation of the adaptive-SNR analog front end. Dedicated DSP with an additional volume control parameter eliminates any internal overflow and enables the hearing aid to be customized for each individual user. When the input audio band is split into a low band and a high band, the audio signal can be processed coarsely. In addition, fine processing of the high-band signal can be obtained with a low-power automatic gain control (AGC) comprising a digital comparator and a subtraction unit. A heterogeneous Sigma-Delta DAC reduces the power consumption of the interpolation filter without degrading performance by allowing different frequencies between the input signal and the sampling clock of the Sigma-Delta modulator. Compared with a conventional Sigma-Delta DAC, the heterogeneous Sigma-Delta DAC reduces the power dissipation by. 40.4% and the area occupation by 40.5%, and it has a reported error rate of only 0.16%. The fabricated chip achieves a 79 dB peak SNR with 4.1 mu Vrms of input-referred noise voltage. The core area is 2.8 mm x 1.1 mu m in a 0.18 mu m standard CMOS process.