DSpace at KOASAS: Experimental Realization of a Full Adder by Substrate Fed Threshold Logic Structure

DSpace at KOASAS

College of Engineering(공과대학)School of Electrical Engineering(전기및전자공학부)EE-Journal Papers(저널논문)

Experimental Realization of a Full Adder by Substrate Fed Threshold Logic Structure

Cited 0 time in webofscience

Cited 0 time in

Hit : 327
Download : 0

Export

C.H.Han / Kim, Choong Ki

Publisher: Inst Engineering Technology-Iet

Issue Date: 1983-08

Language: English

Article Type: Article

Citation: ELECTRONICS LETTERS, v.19, no.16, pp.613 - 615

ISSN: 0013-5194

URI: http://hdl.handle.net/10203/61176

Appears in Collection

Files in This Item: There are no files associated with this item.

Display Full Item Record

qr_code

트윗하기

KOASAS

Knowledge Service Development Team, KAIST 291 Daehak-ro, Yuseong-gu, Daejeon 34141, Republic of Korea. T. 82-42-350-4493 Email. koasas@kaist.ac.kr
Copyright © 2016. Korea Advanced Institute of Science and Technology. All Rights Reserved.

KOASAS

KOASAS

Browse

Experimental Realization of a Full Adder by Substrate Fed Threshold Logic Structure

KOASAS

Communities & Collections