DC Field | Value | Language |
---|---|---|
dc.contributor.author | Chung, Daehyun | - |
dc.contributor.author | Ryu, Chunghyun | - |
dc.contributor.author | Kim, Hyungsoo | - |
dc.contributor.author | Lee, Choonheung | - |
dc.contributor.author | Kim, Jinhan | - |
dc.contributor.author | Bae, Kicheol | - |
dc.contributor.author | Yu, Jiheon | - |
dc.contributor.author | Yoo, Hoijun | - |
dc.contributor.author | Kim, Joungho | - |
dc.date.accessioned | 2007-06-20T09:20:25Z | - |
dc.date.available | 2007-06-20T09:20:25Z | - |
dc.date.issued | 2006-01 | - |
dc.identifier.citation | Solid-state circuits, IEEE Journal of, vol.41. pp. 274-286 | en |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | http://hdl.handle.net/10203/577 | - |
dc.description.abstract | This paper presents a chip-package hybrid clock distribution network and delay-locked loop (DLL) with which to achieve extremely low jitter clock delivery. The proposed hybrid clock distribution network and DLL provide digital noise-free and low-jitter clock signals by utilizing lossless package layer interconnections instead of lossy on-chip global wires with cascaded repeaters. The lossless package layer interconnections become high-frequency waveguides and provide a repeater-free clock distribution network; thus, the clock signal becomes free of on-chip power supply noise. The proposed chip-package hybrid clock scheme has demonstrated a 78-ps peak-to-peak jitter at 500 MHz under a 240-mV on-chip simultaneous switching noise condition versus a conventional clock scheme, which produced a 172-ps peak-to-peak jitter under the same condition. Moreover, the proposed scheme has demonstrated an 80-ps long-term jitter with a 300-mV DC voltage drop test condition, contrasted with the 380-ps long-term jitter of a conventional clock scheme. Finally, the proposed hybrid clock scheme has a confirmed delay of 1.47 ns versus a conventional clock scheme delay of 2.85 ns. | en |
dc.language.iso | en_US | en |
dc.publisher | IEEE | en |
dc.subject | chip-package hybrid clock distribution network | en |
dc.subject | chip-package hybrid delay-locked loop dll | en |
dc.title | Chip-Package Hybrid Clock Distribution Network and DLL for Low Jitter Clock Delivery | en |
dc.type | Article | en |
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