Quasi-3-D velocity saturation model for multiple-gate MOSFETs

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dc.contributor.authorHan, Jin-Wooko
dc.contributor.authorLee, Choong-Hoko
dc.contributor.authorPark, Donggunko
dc.contributor.authorChoi, Yang-Kyuko
dc.date.accessioned2007-06-20T05:55:54Z-
dc.date.available2007-06-20T05:55:54Z-
dc.date.created2012-02-06-
dc.date.created2012-02-06-
dc.date.issued2007-05-
dc.identifier.citationIEEE TRANSACTIONS ON ELECTRON DEVICES, v.54, no.5, pp.1165 - 1170-
dc.identifier.issn0018-9383-
dc.identifier.urihttp://hdl.handle.net/10203/562-
dc.description.abstractThis paper presents a quasi-3-D velocity saturation model for a multiple-gate MOSFET based on a calculation of Gauss's equation. A new and compact velocity saturation region length is derived from a simple approximation of the electric field distribution in the pinchoff region. It is found that the length of the velocity saturation region increases with the increment of gate length and fin width. This new model is used to derive an analytical expression of a substrate current for a trigate MOSFET. In order to improve the accuracy of the substrate current model, the newly derived substrate current model introduces a parasitic potential drop across a thin-extension region and a dimensionless fitting parameter. A body-tied trigate MOSFET is fabricated on a bulk wafer so that the substrate current could be measured by its body contact. The new substrate current model is then compared with measurement data for a trigate MOSFET, and good agreement is observed.-
dc.description.sponsorshipThis work was supported in part by Samsung Electronics Co. Ltd., and in part by the Korea Ministry of Science and Technology under the National Research Program for the 0.1-Terabit Nonvolatile Memory Development.en
dc.languageEnglish-
dc.language.isoen_USen
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.subjectSUBSTRATE CURRENT MODEL-
dc.subjectSIMULATION-
dc.subjectREGION-
dc.titleQuasi-3-D velocity saturation model for multiple-gate MOSFETs-
dc.typeArticle-
dc.identifier.wosid000246033700031-
dc.identifier.scopusid2-s2.0-34247866290-
dc.type.rimsART-
dc.citation.volume54-
dc.citation.issue5-
dc.citation.beginningpage1165-
dc.citation.endingpage1170-
dc.citation.publicationnameIEEE TRANSACTIONS ON ELECTRON DEVICES-
dc.identifier.doi10.1109/TED.2007.894595-
dc.embargo.liftdate9999-12-31-
dc.embargo.terms9999-12-31-
dc.contributor.localauthorChoi, Yang-Kyu-
dc.contributor.nonIdAuthorHan, Jin-Woo-
dc.contributor.nonIdAuthorLee, Choong-Ho-
dc.contributor.nonIdAuthorPark, Donggun-
dc.type.journalArticleArticle-
dc.subject.keywordAuthorcharacteristic length-
dc.subject.keywordAuthorFinFET-
dc.subject.keywordAuthorimpact ionization-
dc.subject.keywordAuthormultiple-gate MOSFET-
dc.subject.keywordAuthorsubstrate current-
dc.subject.keywordAuthortrigate-
dc.subject.keywordAuthorvelocity saturation-
dc.subject.keywordPlusSUBSTRATE CURRENT MODEL-
dc.subject.keywordPlusSIMULATION-
dc.subject.keywordPlusREGION-
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