TraNSIM : a fast, reconfigurable network-on-chip simulator for application-specific MPSoC architectureTraNSIM

Cited 0 time in webofscience Cited 0 time in scopus
  • Hit : 482
  • Download : 0
As the integration technology grows, the demand on high-performance and multiple purpose applications grows as well. These applications require System on Chip architecture with more complex computation power. Multi-processor SoC architecture integrates multiple processors in a chip and enhances the computation power. As well, system is modularized and modularized IPs which are established before are reused. So the time, effort and cost for design are reduced. However, these architectures require additional communication architecture for the communication between processors. Bus is generally used before. But as the number of processors in a chip increases, the performance degradation of system becomes larger because bus has limited bandwidth. So a scalable communication architecture which provides communication bandwidth for multiple processors is required. Network-on-chip is considered as such architecture. Network-on-chip has various configurations and those configurations affect the performance of system. It is important to find the configuration parameters fit for the characteristics of application. Topologies, protocols and the methods for mapping are those configurations. These configurations make infinite combinations of configurations and it is required to evaluate these configurations at the early stage of SoC design. In order to provide the methodology, this work introduces automized and unified simulation environment. The simulator which is named TraNSIM is fast, reconfigurable and extendible simulator. It has three automations. The first is automatic mapping of application. The second is automatic integration of NoC architecture. The third is making simulation code using TraNSIM library. This paper also includes two case studies that apply TraNSIM to the specific applications. First, List Sphere Decoder which is one of MIMO detection scheme for wireless communication is used. Various multi-processor architectures are explored in this case. Secon...
Advisors
Park, Sin-Chongresearcher박신종researcher
Description
한국정보통신대학교 : 공학부,
Publisher
한국정보통신대학교
Issue Date
2006
Identifier
392647/225023 / 020034606
Language
eng
Description

학위논문(석사) - 한국정보통신대학교 : 공학부, 2006, [ viii, 81 p. ]

Keywords

Network on Chip; Transaction Level Model; 트렌젝션 수준 모델; 네트워크 온 칩; SystemC

URI
http://hdl.handle.net/10203/55467
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=392647&flag=dissertation
Appears in Collection
School of Engineering-Theses_Master(공학부 석사논문)
Files in This Item
There are no files associated with this item.

qr_code

  • mendeley

    citeulike


rss_1.0 rss_2.0 atom_1.0