A 2.64-GHz CMOS phase-locked loop for MB-OFDM UWB transceiver

Abstract

Multi-Band Orthogonal Frequency Division Multiplexing Ultra-Wideband (MB-OFDM UWB) is a standard that can communicate at the high data rate, up to 200M/bps, in the short-range such as home networks. The goal of MB-OFDM UWB system is to achieve low complex, low cost, low power consumption and high data rate. Conventional monolithic frequency synthesizer is difficult to fulfill the fast switching time (~1ns) of MB-OFDM UWB specifications, because it is required much wider loop bandwidth without sacrificing phase noise and spur performance of the frequency synthesizer. The proposed method to implement the fast switching frequency synthesizer is to use a phase-locked loop (PLL) to generate a fixed LO frequency and a mixing circuitry to generate other required LO frequencies in parallel. A PLL is dominant block affecting the phase noise and spur of the fast switching frequency synthesizer. This dissertation presents a 2.64GHz CMOS phase-locked loop that meets MB-OFDM UWB specifications such as phase noise and spur. The PLL design employs an integer-N type architecture with a charge pump matched up/down currents and the appropriate loop filter to achieve a optimized phase noise. In addition, the proposed PLL generates I/Q LO signals from the first high frequency divider. Implemented in a 0.18$\mum$ CMOS technology and measured at a 1.8V supply, the result meets phase noise and spur requirement of the MB-OFDM UWB transceiver. Operating at 2.64GHz, the design consumes 22.1mW in core and achieves a phase noise of -113dBc/Hz at 1MHz offset frequency with a loop bandwidth of 100KHz. The chip area is 1300$\mum$ $\times$ 650$\mum$, excluding pads.