This thesis is composed of three topics. The first topic is ``An Effective Polling Scheme and Adaptive Ack Mechanism for IEEE 802.11e.`` This topic is illustrated in part Ⅰ. In this part, an effective polling scheme for the wireless LAN environment has proposed. The proposed polling scheme reduces the number of polling times for a station with no packets to transmit. Therefore, it reduces the amount of time wasted, and improves throughput when some stations in the polling list have packets to transmit. For example, the simulation result shows that the throughput increases by 35.8% when fifteen stations out of thirty stations in the polling list have packets to transmit at IEEE 802.11 a 54Mbps rate. In addition, the adaptive Ack policy improves about 2Mbps of throughput in the same environment.
The second topic is "Accelerating Verification with Reusable Testbench." This topic is shown at part II. This part presents an effective testbench architecture far accelerated verification and reuse of parts of testbench in co-emulation. The testbech is divided into a synthesizable part which can be hardware accelerated and non-synthesizable part which remains on the software simulator. The split blocks of testbench can be reused far other test environment. Experiment with the real world system shows that the proposed verification environment has over 31% higher performance than that of the conventional co-emulation environment. The proposed verification environment as over 31% higher performance than that of the conventional co-emulation environment.
The last topic is ``Model checking for Viterbi decoder.`` This topic is illustrated in part III. The design complexity continues to grow. Verification engineers cannot keep up using only conventional verification methods, such as logic simulation. Therefore, formal verification techniques are required. For sequential systems, one of the most feasible approaches to formal verification is model checking. In this part, the ...