Network on chip architecture exploration and evaluation for wireless communication systems

Abstract

Future multiprocessor system-on-chip (SoC) designs will need novel on chip communication architectures that can provide scalable and reliable data transport. On chip network architectures are believed to be the ideal solution to many of today``s SoC interconnection problems. Switching techniques have a significant Impact on the performance and the behavior of the interconnection network. In part I of this paper, we explore several critical aspects in the physical and network layers of the on-chip communication stack that include the on-chip switching schemes and the impact of the packet header on system performance. Based on analysis of NoC communication architecture and protocol, we evaluate and simulate various switching schemes with C++ based NoC simulator. We propose the effective virtual circuit switching scheme that is hybrid type switching method of circuit switching and packet switching for high throughput, low latency, and low drop rate with small buffer size. The growing complexity of embedded multi-processor architectures for wireless communication systems will soon require highly scalable communication. Current application and technology trends motivate a paradigm shift in on-chip interconnect architectures from bus-based MPSoC to packet switched NoC. In part II of this paper, we propose an architecture exploration and evaluation methodology to help the designer in finding the right NoC communication architecture far wireless communication system design given a set of constraints. In order to evaluate the potential of our methodology for rent applications, we applied this method to IEEE 802.11a system with the tightest constraints of latency and throughput among wireless SoCs. Furthermore, we point out the advantages during the optimization procedure in terms of complexity and energy efficiency that can be obtained by customizing the communication architecture to characteristics of the communication traffic generated by the SoC components.