An implement of clock phase alignment for burst-mode data recovery in gigabit PON systems

Abstract

In this thesis, a broadband Clock Phase Alignment (CPA) for burst mode data recovery in Gigabit Passive Optical Network (PON) systems is studied and designed. This burst mode CPA was implemented based on the over-sampling and tap-selection technique that the imcoming preamble containing a repeated "1010" toggle bit sequence is sampled with multiple clock phases and selects the phase-tap, and verified by the high level simulation technique using Very high speed integrated circuit Hardware Description Language (VHDL). The desinged burst mode CPA shows the feature of the burst acquisition time within 13bits, $\pm 1/8^th$ jitter tolerance [UI], continuous clock output, byte rete ( $\1/8^{th}$ data rate) reference clock input, lock-detected output, LVPECL serial data input and output with 1.25Gbit/s, LVPECL reset input and dc-coupled for burst-mode Gigabit PON applications. We also disigned the burst CPA to be met the standard of the GPON ITU.G984 OLT receiver application and LatticeSC Field Programmable Gate Array (FPGA) are used for experiment of our designed burst mode CPA.