Systematic power optimizing cyclic ADC design

Abstract

A technique for optimizing power dissipation in cyclic Analog-to-Digital Converters (ADC) is presented. Using the Multiplying Digital-to-Analog Converter (MDAC) with proposed capacitor sharing technique, cyclic ADCs configure much reduced power dissipation both Sample-and-Hold Amplifier (S/H) and proposed gm controlling technique, power dissipation of MDAC also optimized. The proposed arrangement technique re-schedules the timing of capacitor between S/H and MDAC to achieving less power dissipation at S/H. Since, limit of sampling capacitor of S/H capacitor usage timing always determined from MDAC’s shared capacitor. And also, with multi-phase clocking technique and multi-size of MDAC cap arrays, MDAC save more power dissipation. This technique can be applied to cyclic ADC including pipelined ADC. This converter requires single S/H, 2.75-bit-MDAC with 3-group capacitor arrays, 3 sub-ADCs, Digital-Error-Correction Logic, and continuous multi-phase clock generator.