A low-power 10~73dB gain control complex filter with complex DC-offset cancellation circuit and automatic frequency tuning circuit

Abstract

This thesis describes a design of CMOS complex filter for low-IF receiver, providing solution of DC-offset problem. Proposed novel DC-offset cancellation circuit, called complex DC-offset cancellation circuit, allows that complex filter can get high gain. In the thesis, the fundamentals of the design of CMOS complex filter are introduced, and design techniques of finding optimum components`` value. Recently low-IF architecture has become a good choice compare to direct conversion architecture, as high performance A/D converter is introduced and digital domain processing techniques are improved. However, complex filter which is used to reject image can not get high gain because of DC-offset problem. This thesis introduces optimized and simple technique to cancel DC-offset with mathematic analysis. As a result, complex filter can get high gain by cancelling DC-offset not only symmetrically but effectively. This can be the model for future design of complex filter hopefully. The filter is implemented by TSMC 0.18 um foundry. The simulation, which is Postlayout in the corner condition, shows 10~73dB linear gain with 1dB step, 2MHz bandwidth at 2MHz center frequency, 7.6dBm of P1dB at minimum gain with 2.4mA current consumption. In addition, it shows 15.4dB NF (@1k ohm source), -4.6dBm outband IIP3, -37dBm in-band IIP3 at maximum gain. This filter can overcome DC-offset until $\plusmn$160mV when single offset or $\plusmn$100mV when both offset and tune frequency automatically although passive components`` value vary $\plusmn$40%.