Optimization of via etching for DRAM application

Abstract

The purpose of this thesis is optimizing via etching process in order to increase the productivity and maintain the stability of via process. It evaluates characteristics of the $0.35\mum$-via hole etching using $C_2$$F_6$ gas, Ar gas and transformer coupled plasma(TCP) source. The samples are films of triple-layer(TEOS/SOG/TEOS) on the 8 inch wafers. And an experiment is designed by orthogonal array matrix, $L_93^4$. The chambers with TCP source are used to carry out the experiment. Such chamber are one kind of HDP(high density plasma). Consequently, the characteristics of $C_2$$F_2$ and Ar gases show the etch rate of $0.8\mum/min$ - $1.1\mum/min$, the uniformity of under $\pm$6.9%, CD difference between pre and post-etching of under 10% and a very good window of profiles. Even though 20sccm flow rate of $C_2$$F_2$ has no SOG recess, 14sccm of $C_2$$F_2$ attacks side wall of SOG. The characteristics of $C_2$$F_2$ and Ar gases result in the fast etch rate and side window of profile. Experiment is done by the orthogonal matrix technique. The results of the experiment are obtained by using 10 wafers. As a result, etch rate, uniformity, critical dimension(CD) variation, selectivity to photo resist(PR), selectivity to TiN and spin on glass(SOG) recess and profiles are satisfied with the requirements of the production process.