A low phase noise CMOS frequency synthesizer design for digital TV applications

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dc.contributor.advisorLee, Sang-Gug-
dc.contributor.advisor이상국-
dc.contributor.authorYun, Seok-Ju-
dc.contributor.author윤석주-
dc.date.accessioned2011-12-28T02:45:06Z-
dc.date.available2011-12-28T02:45:06Z-
dc.date.issued2009-
dc.identifier.urihttp://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=393132&flag=dissertation-
dc.identifier.urihttp://hdl.handle.net/10203/54624-
dc.description학위논문(박사) - 한국정보통신대학교 : 공학부, 2009.2, [ xii, 128 p. ]-
dc.description.abstractWith the increasing demand for high quality TV service, digital television (DTV) is replacing the conventional analog television. DTV tuner is one of the most critical blocks of the DTV receiver system. The trend to implement DTV tuner is achieving small size and low power consumption. Advanced CMOS technology is a good solution to integrate to realize low cost CMOS DTV tuner and CMOS frequency synthesizer is key building blocks in DTV tuner. This dissertation is mainly focused on the analysis and realization of CMOS fractional.N frequency synthesizer for DVB-H and T-DMB mobile DTV tuner systems. In addition, a brief review of conventional VCO and PLL is provided, and design techniques of the DTV fractional-N frequency synthesizer are investigated. Multi-Mode CMOS fractional-N frequency synthesizer is implemented by CMOS 018$\microm$ technology. A fully-integrated CMOS voltage controlled oscillator is included to generate local oscillator signals which cover wide frequency range, 170MHz~ 240MHz (VHF) and 460~870MHz (UHF), 1452~1492MHz/ 1670~1675MHz (L-band). To improve phase noise performance of the frequency synthesizer, a source damping resister is adopted in VCO design. For high speed and wide band operation, divider chains are exploited, and MESH type $3^{rd}$ order delta sigma modulator is developed for low phase noise and fast switching time. The measurement result shows that in-band phase noise is less than -90dBc/Hz and out-band phase noise at 1.25MHz offset is less than -130dBc/Hz over whole frequency band. The calculated integrated phase noise of the synthesizer is about -44dBc. The frequency synthesizer fully covers various frequency band for VHF and UHF band while dissipating from 20mA to 30mA at 1.8V supply. The overall performance of the implemented fractional-N frequency synthesizer is satisfied for the DVB-H, T-DMB and ISDBT standards.eng
dc.languageeng-
dc.publisher한국정보통신대학교-
dc.subject디지털 TV 튜너-
dc.subject위상잡음-
dc.subject전압 제어 발진기-
dc.subject주파수 합성기-
dc.subjectCMOS-
dc.subjectVCO-
dc.subjectVoltage Controlled Oscillator-
dc.subjectPLL-
dc.subjectFreqeuncy synthesizer-
dc.subjectPhase noise-
dc.titleA low phase noise CMOS frequency synthesizer design for digital TV applications-
dc.typeThesis(Ph.D)-
dc.identifier.CNRN393132/225023-
dc.description.department한국정보통신대학교 : 공학부, -
dc.identifier.uid020055178-
dc.contributor.localauthorLee, Sang-Gug-
dc.contributor.localauthor이상국-
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School of Engineering-Theses_Ph.D(공학부 박사논문)
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