CMOS wireless transceiver designs for 5 GHz WLAN and ZigBee

Abstract

This thesis present fully integrated direct conversion transceiver designs for WLAN (IEEE 802.11.a/HiPERLAN2) operating in the frequency band of 5 GHz and ZigBee(IEEE 802.15.4) operating in the 868/915 MHz and 2.4 GHz bands. At first, architectural advantages and disadvantages of superheterodyne, low-intermediate frequency, and direct-conversion scheme is employed to implement lo-cost and highly integrated transceivers. General overview of physical layer radio specifications are discussed for 5GHz WLAN and ZigBee standards. To derive the radio specifications, system level behavioral simulations are performed to see radio performances in terms of bit error rate, packet error rate, error vector magnitude, and signal constellation. The radio specifications include parameters such as noise figure, nonlinearity, channel filtering, phase noise of local oscillator, dynamic range, and bit resolutions of analog-to-digital and digital-to-analog converters. Several circuit topologies are employed to tackle the disadvantages of the direct conversion scheme. Low flicker noise down-conversion mixers and an offset clock generator are employed to tackle the problems of direct conversion scheme for 5 GHz WLAN application. Furthermore, the techniques of employing current reusing and off-chip inductors are adopted to reduce power consumption and die size for ZigBee applications. The radio transceiver chips for 5 GHz WLAN and ZigBee standards are implemented using 0.18$\mum$ CMOS technology. In Appendix A, a wide band on-chip spiral inductor model for radio frequency integrated circuit is introduced, and its model parameter extraction methodology is described.