DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Paik, Kyung-Wook | - |
dc.contributor.advisor | 백경욱 | - |
dc.contributor.author | Nah, Jae-Woong | - |
dc.contributor.author | 나재웅 | - |
dc.date.accessioned | 2011-12-15 | - |
dc.date.available | 2011-12-15 | - |
dc.date.issued | 2004 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=237590&flag=dissertation | - |
dc.identifier.uri | http://hdl.handle.net/10203/49785 | - |
dc.description | 학위논문(박사) - 한국과학기술원 : 신소재공학과, 2004.2, [ xiv, 172 p. ] | - |
dc.description.abstract | Flip chip assembly on organic substrate technology has been developed and implemented as a key packaging technology for cost and performance advantages. When organic substrates are used for the recent high pin count flip chip assembly, substrate bending and warpage problems should be solved to guarantee good flip chip interconnection and high assembly yield. In this dissertation, solder flip chip bumping and subsequent coining processes on organic substrates were investigated to solve the warpage problem of organic substrates for high pin count flip chip assembly by providing good co-planarity. The changes of coining loads in coining processes of solder bumps on organic substrate were investigated by a specially designed coining machine. The reliability of assembled flip chip of 97Pb-3Sn on the chip and coined 37Pb-63Sn on the substrate side was studied to understand the functioning interconnections. The stencil printed bumping process developments are described in Chapter 3. The solder pastes, stencil printing mask, printing method, reflow development steps are optimized for solder bumping on organic substrates. The interfacial reactions between stencil printed solder bumps and organic substrate finished materials have been studied. In chapter 4, the coining process of the stencil printed solder bump on organic substrates has been successfully performed by using a modified tension/compression tester as variables of height, coining rate, and temperature. For the effects of coining process parameters on coining loads, it was found that effects of process temperature and coining rate were significant. In the coining process, applied coining loads become smaller as coining rates decrease and process temperature increases. The flip chip interconnections were successfully demonstrated by the coined 37Pb-3Sn solders on PCB substrate wrapping around 97Pb-3Sn solder bumps on chip at eutectic solder reflow temperature (220℃) in chapter 5. For the electroplated 97Pb-3S... | eng |
dc.language | eng | - |
dc.publisher | 한국과학기술원 | - |
dc.subject | RELIABILITY | - |
dc.subject | ORGANIC SUBSTRATE | - |
dc.subject | FLIP CHIP | - |
dc.subject | SOLDER | - |
dc.subject | ELECTROMIGRATION | - |
dc.subject | electromigration | - |
dc.subject | 신뢰성 | - |
dc.subject | 유기 기판 | - |
dc.subject | 플립칩 | - |
dc.subject | 솔더 | - |
dc.title | Studies on solder bumps coining processes and reliability of assembled flip chip | - |
dc.title.alternative | 솔더 범프 코이닝 공정 및 플립칩 접속 후 신뢰성에 관한 연구 | - |
dc.type | Thesis(Ph.D) | - |
dc.identifier.CNRN | 237590/325007 | - |
dc.description.department | 한국과학기술원 : 신소재공학과, | - |
dc.identifier.uid | 000995809 | - |
dc.contributor.localauthor | Nah, Jae-Woong | - |
dc.contributor.localauthor | 나재웅 | - |
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