Defect-free silicon crystal wafers are excellent substrates for the fabrication of nano-scaled semiconductor memory devices since they are cost-effective rather than epitaxial wafers despite similar qualities. As a matter of factor, more and more device makers have replaced their semiconductor substrates with defect-free silicon crystal wafers. At the same time, they have asked silicon wafer makers of low priced substrates with higher quality. Therefore, some wafer makers have made efforts to reduce the manufacturing cost of defect-free silicon wafers. One of such efforts is increasing the pulling rate to grow the defect-free crystal with sufficient process window. In these points, the process parameters for higher pulling rate have been investigated. In addition, tens of nano-meter-sized small void defects with near defect-free regions have been investigated with transmission electron microscopy study and then the formation mechanism of defect-free crystals has been studied in this thesis.
Singular phenomena of asymmetric microdefect formation behavior have been reported for the first time in the CZ-Si crystals. When the effects of the crystal temperature distributions on the formation behavior of intrinsic point defects are dominant, the final patterns of grown-in microdefects in the crystal are axisymmetric. On the contrary, when the effects of the melt temperature distributions on the formation behavior of intrinsic point defects are dominant, the final patterns of grown-in microdefects in the crystal are asymmetric. This can be attributed to a lack of axisymmetry in spatial v/G profile, which is caused by the asymmetry of the melt temperature distributions at a very low crucible rotation rate < 0.8 rpm. This asymmetry of the melt temperature distributions was confirmed with the cone-shaped shouldering test, where asymmetric formation of {111} crystal facets was found at very low crucible rotation = 0.1 rpm. Therefore, the crucial factor of determining t...