DC Field | Value | Language |
---|---|---|
dc.contributor.author | KIM, HC | ko |
dc.contributor.author | Maeng, SeungRyoul | ko |
dc.contributor.author | Cho, Jung Wan | ko |
dc.date.accessioned | 2008-06-05T06:43:16Z | - |
dc.date.available | 2008-06-05T06:43:16Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 1995-05 | - |
dc.identifier.citation | IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, v.E78D, no.5, pp.586 - 595 | - |
dc.identifier.issn | 0916-8532 | - |
dc.identifier.uri | http://hdl.handle.net/10203/4942 | - |
dc.description.abstract | Motion estimation is a major part of the video coding, which traces the motion of moving objects in video sequences. Among various motion estimation algorithms, the Hierarchical Block-Matching Algorithm (HBMA) that is a multilayered motion estimation algorithm is attractive in motion-compensated interpolation when accurate motion estimation is required. However, parallel processing of HBMA is necessary since the high computational complexity of HBMA prevents it from operating in real-time. Further, the repeated updates of vectors naturally lead to pipelined processing. In this paper, we present a pipelined architecture for HBMA. We investigate the data dependency of HBMA and the requirements of the pipeline to operate synchronously. Each pipeline stage of the proposed architecture consists of a systolic array for the block-matching algorithm, a bilinear interpolator, and a latch mechanism. The latch mechanism mainly resolves the data dependency and arranges the data flow in a synchronous way. The proposed architecture achieves nearly linear speedup without additional hardware cost over a non-pipelined one. It requires the clock of 2.70 ns to process a large size of frame (e.q. HDTV) in real-time, which is about to be available under the current VLSI technology. | - |
dc.language | English | - |
dc.language.iso | en_US | en |
dc.publisher | IEICE-INST ELECTRON INFO COMMUN ENG | - |
dc.title | A DESIGN OF PIPELINED ARCHITECTURE FOR HIERARCHICAL BLOCK-MATCHING ALGORITHM | - |
dc.type | Article | - |
dc.identifier.wosid | A1995RA16500011 | - |
dc.identifier.scopusid | 2-s2.0-0029306233 | - |
dc.type.rims | ART | - |
dc.citation.volume | E78D | - |
dc.citation.issue | 5 | - |
dc.citation.beginningpage | 586 | - |
dc.citation.endingpage | 595 | - |
dc.citation.publicationname | IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS | - |
dc.embargo.liftdate | 9999-12-31 | - |
dc.embargo.terms | 9999-12-31 | - |
dc.contributor.localauthor | Maeng, SeungRyoul | - |
dc.contributor.nonIdAuthor | KIM, HC | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | PARALLEL ARCHITECTURE | - |
dc.subject.keywordAuthor | MOTION ESTIMATION ALGORITHM | - |
dc.subject.keywordAuthor | VIDEO CODING | - |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.