Showing results 1 to 5 of 5
A 320-fs RMS Jitter and-75-dBc Reference-Spur Ring-DCO-Based Digital PLL Using an Optimal-Threshold TDC Seong, Taeho; Lee, Yongsun; Yoo, Seyeon; Choi, Jaehyouk, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.54, no.9, pp.2501 - 2512, 2019-09 |
A Low-Jitter and Low-Reference-Spur Ring-VCO- Based Injection-Locked Clock Multiplier Using a Triple-Point Background Calibrator Yoo, Seyeon; Choi, Seojin; Lee, Yongsun; Seong, Taeho; Lim, Younghyun; Choi, Jaehyouk, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.56, no.1, pp.298 - 309, 2021-01 |
A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop Filter PLL Using a Fast Phase-Error Correction Technique Lee, Yongsun; Seong, Taeho; Yoo, Seyeon; Choi, Jaehyouk, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.53, no.4, pp.1192 - 1202, 2018-04 |
A Low-Reference Spur MDLL-Based Clock Multiplier and Derivation of Discrete-Time Noise Transfer Function for Phase Noise Analysis Tak, Geum-Young; Lee, Kwyro, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.65, no.2, pp.485 - 497, 2018-02 |
A Spur Suppression Technique Using an Edge-Interpolator for a Charge-Pump PLL Choi, Jaehyouk; Kim, Woonyun; Lim, Kyutae, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.20, no.5, pp.969 - 973, 2012-05 |
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