Browse "EE-Journal Papers(저널논문)" by Subject latch
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| A 2-8 GHz Wideband Dually Frequency-Tuned Ring-VCO With a Scalable K-VCO Yoo, Seyeon; Kim, Jae Joon; Choi, Jaehyouk, IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, v.23, no.11, pp.602 - 604, 2013-11 |
| A 20 Gb/s 1 : 4 DEMUX without inductors and low-power divide-by-2 circuit in 0.13 mu m CMOS technology Kim, BG; Kim, Lee-Sup; Byun, S; Yu, HK, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.43, pp.541 - 549, 2008-02 |
| Analysis and Evaluation of a BJT-Based 1T-DRAM Choi, Sung-Jin; Han, Jin-Woo; Moon, Dong-Il; Choi, Yang-Kyu, IEEE ELECTRON DEVICE LETTERS, v.31, no.5, pp.393 - 395, 2010-05 |
| Bilayer Graphene-Hexagonal Boron Nitride Heterostructure Negative Differential Resistance Interlayer Tunnel FET Kang, Sangwoo; Fallahazad, Babak; Lee, Kayoung; Movva, Hema; Kim, Kyounghwan; Corbet, Chris M.; Taniguchi, Takashi; et al, IEEE ELECTRON DEVICE LETTERS, v.36, no.4, pp.405 - 407, 2015-04 |
| HLS-1: A High-Level Synthesis Framework for Latch-Based Architectures Paik, Seung-Whun; Shin, In-Sup; Kim, Tae-Whan; Shin, Young-Soo, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.29, pp.657 - 670, 2010-05 |
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