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| Border-trap characterization in high-kappa strained-si MOSFETs Maji, Debabrata; Duttagupta, S. P.; Rao, V. Rarngopal; Yeo, Chia Ching; Cho, Byung Jin, IEEE ELECTRON DEVICE LETTERS, v.28, no.8, pp.731 - 733, 2007-08 |
| Effect of rapid thermal annealing on the interface trap density between Pt and (Ba,Sr)TiO3 thin film Kwak, DH; Jang, BT; Cha, SY; Lee, JS; Lee, Hee Chul, INTEGRATED FERROELECTRICS, v.17, no.1-4, pp.179 - 186, 1997 |
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