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Showing results 1 to 4 of 4

1
Area-Efficient QC-LDPC Decoder Architecture Based on Stride Scheduling and Memory Bank Division

Kim, Bongjin; Park, In-Cheol, IEICE TRANSACTIONS ON COMMUNICATIONS, v.E96B, no.7, pp.1772 - 1779, 2013-07

2
Energy-Efficient Symmetric BC-BCH Decoder Architecture for Mobile Storages

Hwang, Seokha; Moon, Seungsik; Jung, Jaehwan; Kim, Daesung; Park, In-Cheol; Ha, Jeongseok; Lee, Youngjoo, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I: REGULAR PAPERS, v.66, no.11, pp.4462 - 4475, 2019-11

3
Feasibility of 3D Reconstruction of Neural Morphology Using Expansion Microscopy and Barcode-Guided Agglomeration

Yoon, Young-Gyu; Dai, Peilun; Wohlwend, Jeremy; Chang, Jae-Byum; Marblestone, Adam H.; Boyden, Edward S., FRONTIERS IN COMPUTATIONAL NEUROSCIENCE, v.11, 2017-10

4
Low-Power Parallel Chien Search Architecture Using a Two-Step Approach

Yoo, Hoyoung; Lee, Youngjoo; Park, In-Cheol, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.63, no.3, pp.269 - 273, 2016-03

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