Browse "EE-Journal Papers(저널논문)" by Author Yu, Wonsik
Showing results 1 to 5 of 5
| A 0.22 ps(rms) Integrated Noise 15 MHz Bandwidth Fourth-Order Delta Sigma Time-to-Digital Converter Using Time-Domain Error-Feedback Filter Yu, Wonsik; Kim, KwangSeok; Cho, Seong-Hwan, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.50, no.5, pp.1251 - 1262, 2015-05 |
| A 148fS(rms) Integrated Noise 4 MHz Bandwidth Second-Order Delta Sigma Time-to-Digital Converter With Gated Switched-Ring Oscillator Yu, Wonsik; Kim, KwangSeok; Cho, SeongHwan, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.61, no.8, pp.2281 - 2289, 2014-08 |
| A 9 bit, 1.12 ps Resolution 2.5 b/ Stage Pipelined Time-to-Digital Converter in 65 nm CMOS Using Time-Register Kim, KwangSeok; Yu, Wonsik; Cho, SeongHwan, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.49, no.4, pp.1007 - 1016, 2014-04 |
| A Hybrid-Domain Two-Step Time-to-Digital Converter Using a Switch-Based Time-to-Voltage Converter and SAR ADC Kim, Jungho; Kim, Young-Hwa; Kim, KwangSeok; Yu, Wonsik; Cho, SeongHwan, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.62, no.7, pp.631 - 635, 2015-07 |
| A Second-Order Delta Sigma Time-to-Digital Converter Using Highly Digital Time-Domain Arithmetic Circuits Kim, Dongin; Kim, Kwangseok; Yu, Wonsik; Cho, Seonghwan, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.66, no.10, pp.1643 - 1647, 2019-10 |
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