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Showing results 1 to 7 of 7

1
A low-power CAM using pulsed NAND-NOR match-line and charge-recycling search-line driver

Yang, BD; Kim, Lee-Sup, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.40, pp.1736 - 1744, 2005-08

2
A low-power charge-recycling ROM architecture

Yang, BD; Kim, Lee-Sup, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.11, pp.590 - 600, 2003-08

3
A low-power ROM using charge recycling and charge sharing techniques

Yang, BD; Kim, Lee-Sup, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.38, pp.641 - 653, 2003-04

4
A low-power ROM using single charge-sharing capacitor and hierarchical bit line

Yang, BD; Kim, Lee-Sup, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.14, pp.313 - 322, 2006-04

5
A low-power SRAM using hierarchical bit line and local sense amplifiers

Yang, BD; Kim, Lee-Sup, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.40, pp.1366 - 1376, 2005-06

6
An 800-MHz low-power direct digital frequency synthesizer with an on-chip D/A converter

Yang, BD; Choi, JH; Han, SH; Kim, Lee-Sup; Yu, HK, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.39, pp.761 - 774, 2004-05

7
Low-power charge-sharing ROM using dummy bit lines

Yang, BD; Kim, Lee-Sup, ELECTRONICS LETTERS, v.39, no.14, pp.1041 - 1042, 2003-07

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