Showing results 1 to 8 of 8
Clock Gating Synthesis of Pulsed-Latch Circuits Paik, Seung-Whun; Han, In-Hak; Kim, Sang-Min; Shin, Young-Soo, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.31, no.7, pp.1019 - 1030, 2012-07 |
HLS-1: A High-Level Synthesis Framework for Latch-Based Architectures Paik, Seung-Whun; Shin, In-Sup; Kim, Tae-Whan; Shin, Young-Soo, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.29, pp.657 - 670, 2010-05 |
HLS-dv: A High-Level Synthesis Framework for Dual-Vdd Architectures Shin, In-Sup; Paik, Seung-Whun; Shin, Dong-Wan; Shin, Young-Soo, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.20, no.4, pp.593 - 604, 2012-04 |
Pulse Width Allocation and Clock Skew Scheduling: Optimizing Sequential Circuits Based on Pulsed Latches Lee, Hye-In; Paik, Seung-Whun; Shin, Young-Soo, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.29, no.3, pp.355 - 366, 2010-03 |
Pulsed-Latch Circuits: A New Dimension in ASIC Design Shin, Young-Soo; Paik, Seung-Whun, IEEE DESIGN TEST OF COMPUTERS, v.28, pp.50 - 57, 2011 |
Retiming Pulsed-Latch Circuits with Regulating Pulse Width Paik, Seung-Whun; Lee, Seong-Gwan; Shin, Young-Soo, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.30, no.8, pp.1114 - 1127, 2011-08 |
SAMPLING CORRELATION SOURCES FOR TIMING YIELD ANALYSIS OF SEQUENTIAL CIRCUITS WITH CLOCK NETWORKS Yu, Lee-Eun; Shin, Chang-Sik; Paik, Seung-Whun; Liou, Jing-Jia; Shin, Young-Soo, JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, v.20, no.8, pp.1547 - 1569, 2011-12 |
Semicustom Design of Zigzag Power-Gated Circuits in Standard Cell Elements Shin, Young-Soo; Paik, Seung-Whun; Kim, Hyung-Ock, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.28, no.3, pp.327 - 339, 2009-03 |
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