Showing results 1 to 3 of 3
Pulsed-Latch Aware Placement for Timing-Integrity Optimization Chuang, Yi-Lin; Kim, Sangmin; Shin, Youngsoo; Chang, Yao-Wen, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.30, no.12, pp.1856 - 1869, 2011-12 |
Synthesis of Dual-Mode Circuits Through Library Design, Gate Sizing, and Clock-Tree Optimization Kim, Sangmin; Kang, Seokhyeong; Shin, Youngsoo, ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, v.21, no.3, 2016-07 |
Wakeup scheduling and its buffered tree synthesis for power gating circuits Kim, Sangmin; Paik, Seungwhun; Kang, Seokhyeong; Shin, Youngsoo, INTEGRATION-THE VLSI JOURNAL, v.53, pp.157 - 170, 2016-03 |
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