Showing results 1 to 5 of 5
Hybrid L2 NUCA Design and Management Considering Data Access Latency, Energy Efficiency, and Storage Lifetime Lee, Seunghan; Kang, Kyungsu; Jung, Jongpil; Kyung, Chong-Min, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.24, no.10, pp.3118 - 3131, 2016-10 |
Runtime Power Management of 3-D Multi-Core Architectures Under Peak Power and Temperature Constraints Kang, Kyungsu; Kim, Jungsoo; Yoo, Sungjoo; Kyung, Chong-Min, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.30, no.6, pp.905 - 918, 2011-06 |
Runtime Thermal Management for 3-D Chip-Multiprocessors With Hybrid SRAM/MRAM L2 Cache Lee, Seung Han; Kang, Kyungsu; Kyung, Chong-Min, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.23, no.3, pp.520 - 533, 2015-03 |
Three-Dimensional Integration Approach to High-Density Memory Devices Kim, Hojung; Jeon, Sanghun; Lee, Myoung-Jae; Park, Jaechul; Kang, Sangbeom; Choi, Hyun-Sik; Park, Churoo; et al, IEEE TRANSACTIONS ON ELECTRON DEVICES, v.58, no.11, pp.3820 - 3828, 2011-11 |
Vertical InGaAs Biristor for Sub-1 V Operation Kim, Wu-Kang; Bidenko, Pavlo; Kim, Jongmin; Sim, Jaeho; Han, Joon-Kyu; Kim, Seongkwang; Geum, Dae-Myeong; et al, IEEE ELECTRON DEVICE LETTERS, v.42, no.5, pp.681 - 683, 2021-05 |
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