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| NO | Title, Author(s) (Publication Title, Volume Issue, Page, Issue Date) |
|---|---|
| Expandable Analog Neural Network Chip Set With on-Chip Learning by Error Back-Propagation and Hebbian Learning Rules Cho, J.W.; Choi, Y.K.; Kwon, S.O.; Lee, Soo-Young, World Congress on Neural Networks, pp.468 - 471, 1995-07 | |
| Analog Electronic Neuro-Chip Sets with On-Chip Learning Capability Choi, Y.K.; Cho, J.; Lee, Soo-Young, International Symposium on Bioelectronic and Molecular Electronic Devices, pp.259 - 260, 1995-11 | |
| A Neural Chip with Inner-Product Characteristics and Multi-Layer Neural network Board Choi, Y.K.; Park, J.B.; Lee, Soo-Young, 3rd Annual Meeting and Conf. Neurla Networks Study Group, pp.69 - 74, 1992-07 | |
| VLSI Implementaion of Radial Basis Fuction Network with Learning Capability Choi, Y.K.; Cho, J.; Lee, Soo-Young, International Conference on Neural Information Processing, pp.1341 - 1346, 1995-10 | |
| VLSI Implementation of Multi-Layer Bidirectional Associative Memory Choi, Y.K.; Jeong, D.G.; Lee, Soo-Young, 2nd Annual Meeting of Korean Neural Network Study Group, 1991-06 | |
| Implementation of 224x224 Neural Hardware Using Expandable 32x32 MBAM Neuro-Chip Choi, Y.K.; Cho, J.W.; Lee, Soo-Young, 94 FAN Spring, pp.397 - 400, 1994-05 | |
| Modular Analog Neuro-Chip Set with on-Chip Learning by Error-Backpropagation and/or Hebbian Rules Cho, J.; Choi, Y.K.; Lee, Soo-Young, International Conference on Artificial Neural Networks, pp.25 - 29, 1994-06 | |
| Subthreshold MOS Implementaion of Neural Networks with On-Chip Error back-propagation Learning Choi, Y.K.; Lee, Soo-Young, International Joint Conference Neural Networks, pp.25 - 29, 1993-10 |