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| NO | Title, Author(s) (Publication Title, Volume Issue, Page, Issue Date) |
|---|---|
| Co-development of Media-processor and Source-level Debugger using Emulation-based Validation Kyung, Chong-Min; Im, Y.H.; Nam, S.J.; Kim, B.W.; Kang, K.G.; Lee, D.H.; Yang, J.H.; Kwon, Y.S.; Lee, J.H., International Conference on VLSI and CAD(ICVC'99), pp.95 - 98, 1999-10 | |
| A Hardware Accelerator for Phong Illumination Model in 3-Dimentional Grahpics Kwon, Y.S.; Park, In-Cheol; Kyung, Chong-Min, HUMANTECH, pp.277 - 285, 1999 | |
| DIVA:Dual-Issue VLIW Architecture with Media Instructions for Image Processing Nam, S.J.; Kwon, Y.S.; Park, In-Cheol; Kyung, Chong-Min, 대한전자공학회 CAD 및 VLSI 설계연구회 학술발표회, pp.117 - 122, 대한전자공학회, 1999 | |
| FLOVA:A Four0-Issue Media Processor with 3D Geometry Kyung, Chong-Min; Nam, S.J.; Kwon, Y.S.; Kim, B.W.; Im, Y.H.; Kang, K.G., International Conference on Signal Processing Application and Technology(ICSPAT), 1999-11 | |
| VLIW Geometry Processor for 3D Graphics Accelearation Kyung, Chong-Min; Nam, S.J.; Kim, B.W.; Im, Y.H.; Kwon, Y.S.; Kang, K.G., Cool Chips II, pp.107 - 120, 1999-04 | |
| MDSP-II: 16-bit DSP with mobile communication accelerator Kim, B.W.; Yang, J.H.; Kwon, Y.S.; Lee, K.M.; Kim, I.H.; Hwang, C.S.; Lee, D.H.; Lee, J.Y.; Kim, J.S.; Yoon, H.D.; Kim, J.S.; Park, K.I.; Park, K.H.; Lee, Yong-Hoon; Hwang, S.H.; Kyung, Chong-Min, Proceedings of the 1998 IEEE Custom Integrated Circuits Conference, pp.5 - 8, IEEE, 1998-05-11 | |
| MetaCore: An application specific DSP development system Yang, J.H.; Kim, B.W.; Nam, S.J.; Cho, J.H.; Seo, S.W.; Ryu, C.H.; Kwon, Y.S.; Lee, D.H.; Lee, J.Y.; Kim, J.S.; Yoon, H.D.; Kim, J.Y.; Lee, K.M.; Hwang, C.S.; Kim, I.H.; Kim, J.S.; Park, K.I.; Park, K.H.; Lee, Y.H.; Kyung, Chong-Min; Park, In-Cheol; Hwang, Seung-Ho, 35th Design Automation Conference, pp.800 - 803, IEEE, 1998-06 | |
| A New Single-Clock Flip-Flop for Half-Swing Clocking Kwon, Y.S.; Park, B.I.; Park, In-Cheol; Kyung, Chong-Min, ASP-DAC'99, pp.117 - 120, ASP-DAC, 1999-01 |