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Results 1-10 of 17 (Search time: 0.006 seconds).
| NO | Title, Author(s) (Publication Title, Volume Issue, Page, Issue Date) |
|---|---|
| Verification of A Microprocessor Using Real World Applications Chang, Y.S.; Lee, S.J.; Kyung, Chong-Min; Park, In-Cheol, IEEE International High Level Design Validation and Test Workshop(HLDVT'98), pp.204 - 210, IEEE, 1998-11 | |
| Virtual Chip : Making Funcional Models Work on Real Taget Systems Kim, N; Choi, H; Lee, S; Lee, S.W.; Park, In-Cheol; Kyung, Chong-Min, Proceedings of the 1998 35th Design Automation Conference, pp.170 - 173, 1998-06-15 | |
| Track Minimization for the Datapath Layout Compiler Using the Hybrid Genetic Algorithm and Simulated Annealing Kyung, Chong-Min; Yim, J.S., SASIMI'98, pp.39 - 43, 1998-10 | |
| Issues in the Design of the Marcia Internal Cache Chang, Y.S.; Park, In-Cheol; Kyung, Chong-Min, International Conference on Chip Technology, 1998-04 | |
| ACCENT : A CISC-Type Configurable Processor Core Chang, Y.S.; Park, B.I.; Yang, W.S.; Oh, H.S.; Park, In-Cheol; Kyung, Chong-Min, '98 ASIC ON PROCEEDINGS, pp.195 - 198, 1998-10 | |
| A Fast Sine/Cosine Generator with Pipelined CORDIC and Table Lookup Method Shin, M.C.; Park, B.I.; Park, In-Cheol; Kyung, Chong-Min, '98 ASIC ON PROCEEDINGS, pp.281 - 284, 1998-10 | |
| Fast Functional Simulation using Suppressed BDDs Kim, B.W.; Park, In-Cheol; Kyung, Chong-Min, SASIMI'98, pp.96 - 100, 1998-10 | |
| Fast heuristics for optimal CMOS functional cell layout generation Kwon, Yong-Joon; Kyung, Chong-Min, 1988 IEEE International Symposium on Circuits and Systems, Proceedings, v.3, pp.2423 - 2426, IEEE, 1998-06 | |
| An Efficient Approach to Functional Verification of Complex Processors Lee, S.J.; Won, N.R.; Cho, H.C.; Park, B.I.; Chang, Y.S.; Park, S.I.; Park, In-Cheol; Kyung, Chong-Min, International Conference on Chip Technology, 1998-04 | |
| HDL Saver Allowing Restrat after Souce Modification Chang, Y.S.; Lee, S.J.; Park, In-Cheol; Kyung, Chong-Min, APCHDL'98, pp.23 - 27, 1998-07 |
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