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| NO | Title, Author(s) (Publication Title, Volume Issue, Page, Issue Date) |
|---|---|
| A 36 Heterogeneous Core Architecture with Resource-Aware Fine-grained Task Scheduling for Feedback Attention based Object Recognition Lee, Seungjin; Oh, Jinwook; Kim, Minsu; Park, Joonyoung; Kwon, Joonsoo; Kim, Joo-Young; Yoo, Hoi-Jun, Cool Chips 2010, Institute of Electrical and Electronics Engineers Inc., 2010-04-14 | |
| A 1.2mW on-line learning mixed mode intelligent inference engine for robust object recognition Oh, Jinwook; Lee, Seungjin; Kim, Minsu; Kwon, Joonsoo; Park, Junyoung; Kim, Joo-Young; Yoo, Hoi-Jun, 2010 24th Symposium on VLSI Circuits, VLSIC 2010, pp.17 - 18, Institute of Electrical and Electronics Engineers Inc., 2010-06-16 | |
| Z-PIM: An Energy-Efficient Sparsity Aware Processing-In-Memory Architecture with Fully-Variable Weight Precision Kim, Ji-Hoon; Lee, Juhyoung; Lee, Jinsu; Yoo, Hoi-Jun; Kim, Joo-Young, 2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020, Institute of Electrical and Electronics Engineers Inc., 2020-06-16 | |
| Intelligent NoC with neuro-fuzzy bandwidth regulation for a 51 IP object recognition processor Lee, Seungjin; Oh, Jinwook; Kim, Minsu; Park, Junyoung; Kwon, Joonsoo; Kim, Joo-Young; Yoo, Hoi-Jun, 32nd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2010, Institute of Electrical and Electronics Engineers Inc., 2010-09-19 |
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