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Results 1-10 of 46 (Search time: 0.009 seconds).
| NO | Title, Author(s) (Publication Title, Volume Issue, Page, Issue Date) |
|---|---|
| Effect of ground guard fence with via and ground slot on radiated emission in multi-layer digital printed circuit board Lee, H.; Kim, J.; Ahn, S.; Byun, J.-G.; Kang, D.-S.; Choi, C.-S.; Hwang, H.-J.; Kim, Joungho, 2001 IEEE International Symposium on Electromagnetic Compatibility, v.1, pp.653 - 656, IEEE, 2001-08-13 | |
| Slot transmission line model of interconnections crossing split power/ground plane on high-speed multi-layer board Kim, Joungho; Kim, H.; Jeong, Y.; Lee, J.; Kim, J., 6th IEEE Workshop on Signal Propagation on Interconnects, SPI, pp.23 - 26, 2002-05-12 | |
| Design guidelines of spread spectrum clock for suppression of radiation and interference from high-speed interconnection line Kim, J.; Jun, P.; Byun, J.-G.; Kim, Joungho, 6th IEEE Workshop on Signal Propagation on Interconnects, SPI, pp.189 - 192, IEEE, 2002-05-12 | |
| Effect of power/ground partitioning and stitching capacitor placement on signal integrity and emi of multi-layer and multi power system Kim, Joungho; Kim, H.; Lee, H.; Kim, J.; Kim, J., Pacific Rim/International, Intersociety Electronic Packaging Technical/Business Conference and Exhibition, v.1, pp.59 - 62, 2001-07-08 | |
| An evaluation of differential impedance in PCBs using two single-ended probes only Kam, D.G.; Lee, H.; Ryu, W.; Kim, J.; Park, B.; Kim, Joungho, 6th IEEE Workshop on Signal Propagation on Interconnects, SPI, pp.169 - 171, IEEE, 2002-05-12 | |
| A compact, low-cost, and wide-band passive equalizer design using multi-layer PCB parasitics Song, E.; Kim, J.; Kim, Joungho; Cho, J., 2010 IEEE 19th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2010, pp.165 - 168, IEEE, 2010-10-25 | |
| TSV modeling and noise coupling in 3D IC Kim, Joungho; Cho, J.; Kim, J., 3rd Electronics System Integration Technology Conference, ESTC 2010, ESTC 2010, 2010-09-13 | |
| Analysis of power distribution network in TSV-based 3D-IC Kim, K.; Lee, W.; Kim, J.; Song, T.; Kim, J.; Pak, J.S.; Kim, Joungho; Lee, H.; Kwon, Y.; Park, K., 2010 IEEE 19th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2010, pp.177 - 180, IEEE, 2010-10-25 | |
| A chip-package hybrid DLL loop and clock distribution network for low-jitter clock delivery Chung, D.; Ryu, C.; Kim, H.; Lee, C.; Kim, J.; Kim, J.; Bae, K.; Yu, J.; Lee, S.; Yoo, H.; Kim, Joungho, 2005 IEEE International Solid-State Circuits Conference, ISSCC, v.48, pp.514 - 614, 2005-02-06 | |
| I/O power estimation and analysis of high-speed channels in Through-Silicon Via (TSV)-based 3D IC Kim, Joungho; Cho, J.; Pak, J.S.; Song, T.; Kim, J.; Lee, H.; Lee, J.; Park, K., 2010 IEEE 19th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2010, pp.41 - 44, IEEE, 2010-10-25 |