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Results 41-50 of 385 (Search time: 0.009 seconds).

NO Title, Author(s) (Publication Title, Volume Issue, Page, Issue Date)
41
A 210mW graphics LSI implementing full 3D pipeline with 264Mtexels/s texturing for mobile multimedia applications

Woo, R.; Cho,i S.; Sohn, J.-H.; Song, S.-J.; Bae, Y.-D.; Yoon, C.-W.; Nam, B.-G.; Woo, J.-H.; Kim, S.-E.; Park, In-Cheol; Shin, S.; Yoo, K.-D.; Chung, J.-Y.; Yoo, Hoi-Jun, 2003 Digest of Technical Papers, 2003-02-09

42
Autonomous gain verification algorithm for a dual mode digital hearing aid chip

Kim, S.; Yan, L.; Kim, M.; Bae, J.; Yoo, Hoi-Jun, 30th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, EMBS'08, v.2008, pp.2337 - 2340, 2008-08-20

43
A 0.9-v 67-uw analog front-end using adaptive-SNR technique for digital hearing aid

Kim, S.; Lee, J.-Y.; Song, S.-J.; Cho, N.; Yoo, Hoi-Jun, IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005, pp.740 - 743, 2005-05-23

44
An energy-efficient analog front-end circuit for a sub-1V digital hearing aid chip

Kim, S.; Lee, J.-Y.; Song, S.-J.; Cho, N.; Yoo, Hoi-Jun, 2005 Symposium on VLSI Circuits, v.2005, pp.176 - 179, 2005-06-16

45
An autonomous SRAM with on-chip sensors in an 80nm double stacked cell technology

Sohn, K.; Cho, N.; Kim, H.; Kim, K.; Mo, H.-S.; Suh, Y.-H.; Byun, H.-G.; Yoo, Hoi-Jun, 2005 Symposium on VLSI Circuits, v.2005, pp.232 - 235, 2005-06-16

46
A Low-Power and High-Performance 2D/3D Graphics Accelerator for Mobile Multimedia Applications

Yoo, Hoi-Jun; Woo, R; Choi, SD; Sohn, JH; Song, SJ; Bae, YD, IEEE Hot Chips 2003, 2003-08

47
An Analysis and Implementation of High Fairness Arbitration Mechanism by Using Level-table and Static Priority Orders in Shared Bus Architecture

Yoo, Hoi-Jun; Suh, JS, IP Based Design 2003, pp.293 - 296, 2003-11

48
A 10Gbps/port 8x8 Shared Bus Switch with embedded DRAM Hierarchical Output Buffer

Yoo, Hoi-Jun, IEEE ESSCIRC 2003, pp.461 - 464, 2003-09

49
A High-Speed and Lightweight On-Chip Crossbar Switch Scheduler for On-Chip Interconnection Networks

Yoo, Hoi-Jun; Lee, KM; Lee, SJ, IEEE ESSCIRC 2003, pp.453 - 456, 2003-09

50
A 372ps 64-bit adder using fast pull-up logic in 0.18-um CMOS

Kim, J.; Lee, K.; Yoo, Hoi-Jun, ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, pp.13 - 16, 2006-05-21

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