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Results 31-40 of 366 (Search time: 0.003 seconds).

NO Title, Author(s) (Publication Title, Volume Issue, Page, Issue Date)
31
An arbitration look-ahead scheme for reducing end-to-end latency in networks on chip

Kim, K.; Lee, S.-J.; Lee, K.; Yoo, Hoi-Junresearcher, IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005, pp.2357 - 2360, 2005-05-23

32
A 10-uW digital signal processor with adaptive-SNR monitoring for a sub-1V digital hearing aid

Yoo, J.; Kim, S.; Cho, N.; Song, S.-J.; Yoo, Hoi-Junresearcher, ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, pp.3361 - 3364, 2006-05-21

33
Low Power MPEG-4 Video Codec Hardware for Portable Applicatons

Yoo, Hoi-Junresearcher; Yoon, Chi-Weon, CoolChips, pp.77 - 88, 2002

34
7.1GB/sec Bandwidth 3D Rendering Engine Using the EML Technology

Yoo, Hoi-Junresearcher; Park, Yong-Ha; Woo, Ramchan; Han, Seon-Ho; Kim, Jung-Su; Lee, Se-Joong; Kook, Jeong-Hoon; Lim, Jae-Won, International Conference on VLSI and CAD, pp.277 - 280, 1999

35
A Fast Lock-On Time Mixed Mode DLL with 10ps Jitter

Yoo, Hoi-Junresearcher; Han, Seon-Ho; Lee, Joo-Ho, International Conference on VLSI and CAD, pp.564 - 565, 1999

36
POPeye:A System Analysis Tool for DRAM Performance Measurement

Yoo, Hoi-Junresearcher; Im, Yon-Kyun; Yoon, Chiwoen; Jung, Tae-Sung, International Conference on VLSI and CAD, pp.590 - 592, 1999

37
A reconfigurable multilevel parallel graphics cache memory with 75 GB/s parallel cache replacement bandwidth

Park, S.-J.; Kim, J.-S.; Woo, R.; Lee, S.-J.; Lee, K.-M.; Yang, T.-H.; Jung, J.-Y.; Yoo, Hoi-Junresearcher, 2001 VLSI Circuits Symposium, pp.233 - 236, IEEE, 2001-06-14

38
A Fixed-Point 3D Graphics Library with Energy-Efficient Cache Architecture for Mobile Multimedia Systems

Yoo, Hoi-Junresearcher; Lee, MW; Nam, BG; Sohn, JH; Cho, NJ; Kim, HJ; Kim, SH, IEEE ISCAS 2005, pp.4602 - 4605, 2005-05

39
A low power 16-bit RISC with lossless compression accelerator for body sensor network system

Kim. H.; Choi. S.; Yoo, Hoi-Junresearcher, 2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006, pp.207 - 210, 2006-11-13

40
670 ps, 64 bit dynamic low-power adder design

Woo, Ramchan; Lee, Se-Joong; Yoo, Hoi-Junresearcher, Proceedings of the IEEE 2000 Internaitonal Symposium on Circuits and Systems, v.1, 2000-05-28

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