Results 11-20 of 385 (Search time: 0.009 seconds).
NO | Title, Author(s) (Publication Title, Volume Issue, Page, Issue Date) |
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A Fast Synchronous Pipelined DRAM(SP-DRAM) Architecture with SRAM Buffers Yoo, Hoi-Jun; Yoon, Chi-Woen; Im, Yon-Kyun; Han, Seon-Ho; Jung, Tae-Sung, International Conference on VLSI and CAD, pp.285 - 288, 1999 | |
The CMOS Temperature Sensor and Cyclic ADC for Low Power Single Chip DTCXO Yoo, Hoi-Jun; Lee, Joo-Ho; Han, Seon-Ho, International Conference on VLSI and CAD, pp.599 - 601, 1999 | |
A VPM Architecture for a Fast Row-Cycle DRAM Yoo, Hoi-Jun; Yoon, Chi-Woen; Im, Yon-Kyun; Han, Seon-Ho; Jung, Tae-Sung, IEEE Asia Pacific Conference on ASICs, pp.388 - 391, 1999 | |
A Low Noise Folded Bit-Line Sensing Architecture for Multi-Gb DRAM with Ultra High Density 6F2 Cell Yoo, Hoi-Jun, , 1997 | |
A Compact Ring Delay Line for Low Power High Speed Synchronous DRAM Yoo, Hoi-Jun, 98 Synmposium of VLSI Circuits, 1998 | |
A Low Noise 32bit-Wide 256M Synchronous DRAM with Column Decoded I/O Line Yoo, Hoi-Jun, 95 Symp. of VLSI Circuits, 1995 | |
A 150MHz 8-Banks 256M Synchronous DRAM with the Wave Pipelining Method Yoo, Hoi-Jun, 95 IEEE Int. Solid State Circuit Conf., 1995 | |
A Comparative Analysis of a DDR-SDRAM and a D-RDRAM usind a POPeye Simulator Yoo, Hoi-Jun; Lee, K.; Yoon, C.W.; Woo, R.; Kook, J., IEEE International Symposium on Circuits and Systems, pp.v81 - v84, IEEE, 2001 | |
A 7.1GB/s low-power 3D rendering engine in 2D array-embedded memory logic CMOS Park, Y.-H.; Han, S.-H.; Kim, J.-S.; Lee, S.-J.; Kook, J.-H.; Lim, J.-W.; Woo, R.; Yoo, Hoi-Jun; Lee, J.-H.; Lee, J.-H., 2000 IEEE International Solid-State Circuits Conference 47th Annual ISSCC, pp.242 - 243, 2000-02-07 | |
A 24.2-uW dual-mode human body communication controller for body sensor network Choi, S.; Song, S.-J.; Sohn, K.; Kim, H.; Kim, J.; Cho, N.; Woo, J.-H.; Yoo, J.; Yoo, Hoi-Jun, ESSCIRC 2006 - 32nd European Solid-State Circuits Conference, pp.227 - 230, 2006-09-19 |
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