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Results 11-20 of 82 (Search time: 0.007 seconds).
| NO | Title, Author(s) (Publication Title, Volume Issue, Page, Issue Date) |
|---|---|
| A New Layout Scheme for Macro Cells Kyung, Chong-Min; Lee, P.H., International Conference on VLSI and CAD, 1991-10 | |
| Vertical Partitioing of Row-Based Circuits with Minimal Net-Crossings Park, In-Cheol; Kyung, Chong-Min, IEEE International Sympoisum on Circuits and Systems, 1991-06 | |
| Near Optimal Scheduling in Automatic Data Path Synthesis Park, In-Cheol; Kyung, Chong-Min, Joint Technical Conference on Circuits/Systems, Computers and Communications, pp.305 - 310, 대한전자공학회, 1990 | |
| C-based RTL design verification methodology for complex microprocessor Yim, JS; Hwang, YH; Park, CJ; Choi, H; Yang, WS; Oh, HS; Park, In-Cheol; Kyung, Chong-Min, Proceedings of the 1997 34th Design Automation Conference, pp.83 - 88, 1997-06-09 | |
| Two-way partitioning based on direction vector Seong, K.S.; Kyung, Chong-Min, Proceedings of the 1997 European Design & Test Conference, pp.306 - 310, 1997-03-17 | |
| Track Minimization for the Datapath Layout Compiler Using the Hybrid Genetic Algorithm and Simulated Annealing Kyung, Chong-Min; Yim, J.S., SASIMI'98, pp.39 - 43, 1998-10 | |
| SEC: A simple and effective netlist clustering Seong, K.S.; Kyoung, S.J.; Kyung, Chong-Min, Proceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4), v.3, pp.1688 - 1691, 1997-06-09 | |
| A New Pin Assignment Algorithm for Building Block Layout Kyung, Chong-Min; Choi, S.G., JTC-CSCC, 1992-07 | |
| Design verification of complex microprocessors Yim, J; Park, C; Yang, W; Oh, H; Choi, H; Lee, S; Won, N; Park, In-Cheol; Kyung, Chong-Min, Proceedings of the 1996 IEEE Asia Pacific Conference on Circuits and Systems, pp.441 - 448, 1996-11-18 | |
| Issues in the Design of the Marcia Internal Cache Chang, Y.S.; Park, In-Cheol; Kyung, Chong-Min, International Conference on Chip Technology, 1998-04 |