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Showing results 1 to 11 of 11

1
A 47.4µJ/epoch Trainable Deep Convolutional Neural Network Accelerator for In-Situ Personalization on Smart Devices

Choi, Seungkyu; Sim, Jaehyeong; Kang, Myeonggu; Choi, Yeongjae; Kim, Hyeonuk; Kim, Lee-Sup, 2019 IEEE Asian Solid-State Circuits Conference, IEEE/SSCS, 2019-11-05

2
A Kernel Decomposition Architecture for Binary-weight Convolutional Neural Netwarks

Kim, Hyeonuk; Sim, Jaehyeong; Choi, Yeongjae; Kim, Lee-Sup, 54th ACM/EDAC/IEEE Design Automation Conference (DAC), ACM Special Interest Group on Design Automation (SIGDA), 2017-06

3
A PVT-robust Customized 4T Embedded DRAM Cell Array for Accelerating Binary Neural Networks

Shin, Hyein; Sim, Jaehyeong; Lee, Daewoong; Kim, Lee-Sup, 2019 ACM/IEEE International Conference On Computer Aided Design, IEEE/ACM, 2019-11-06

4
An Energy-efficient Processing-in-memory Architecture for Long Short Term Memory in Spin Orbit Torque MRAM

Kim, Kyeonghan; Shin, Hyein; Sim, Jaehyeong; Kang, Myeonggu; Kim, Lee-Sup, 38th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2019, IEEE/ACM, 2019-11-06

5
eSRCNN: A Framework for Optimizing Super-Resolution Tasks on Diverse Embedded CNN Accelerators

Jung, Youngbeom; Choi, Yeongjae; Sim, Jaehyeong; Kim, Lee-Sup, 38th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2019, IEEE/ACM, 2019-11-04

6
NAND-Net: Minimizing Computational Complexity of In-Memory Processing for Binary Neural Networks

Kim, Hyeonuk; Sim, Jaehyeong; Choi, Yeongjae; Kim, Lee-Sup, 2019 IEEE International Symposium on High-Performance Computer Architecture, pp.661 - 673, IEEE/ACM, 2019-02

7
NID: Processing Binary Convolutional Neural Network in Commodity DRAM

Sim, Jaehyeong; Seol, Hoseok; Kim, Lee-Sup, 2018 ACM/IEEE International Conference On Computer Aided Design, pp.10:1 - 10:8, IEEE/ACM, 2018-11-05

8
PowerField: a transient temperature-to-power technique based on Markov random field theory

Paek, Seungwook; Moon, Seok-Hwan; Shin, Wongyu; Sim, Jaehyeong; Kim, Lee-Sup, 2012 Design Automation Conference (DAC), pp.630 - 635, ACM/IEEE, 2012-06-06

9
SENIN: An energy-efficient sparse neuromorphic system with on-chip learning

Choi, Myung-Hoon; Choi, Seungkyu; Sim, Jaehyeong; Kim, Lee-Sup, 22nd IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), IEEE-CAS and ACM-SIGDA, 2017-07-25

10
Timing error masking by exploiting operand value locality in SIMD architecture

Sim, Jaehyeong; Park, Jun-Seok; Paek, Seung-Wook; Kim, Lee-Sup, 32nd IEEE International Conference on Computer Design, ICCD 2014, pp.90 - 96, IEEE Circuits and Systems Society, 2014-10

11
TrainWare: A Memory Optimized Weight Update Architecture for On-Device Convolutional Neural Network Training

Choi, Seungkyu; Sim, Jaehyeong; Kang, Myeonggu; Kim, Lee-Sup, 23rd IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pp.104 - 109, ACM/IEEE, 2018-07-24

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