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Showing results 1 to 6 of 6

1
A Programmable Turbo Decoder for Multiple Third-Generation Wireless Standards

Park, In-Cheol; Shin, MC, International Solid-State Circuits Conference, ISCC, 2003-02-13

2
A Two-step 5b Logarithmic ADC with Minimum Step-size of 0.1% Full-scale for MLC Phase-Change Memory Readout

Kwon, JW; Jin, DH; Kim, HJ; Hwang, SI; Shin, MC; Kang, JH; Ryu, Seung-Tak, Custom Integrated Circuits Conference(CICC), IEEE, 2014-09-17

3
An Area-Efficient Iterative Modified-Booth Multiplier Based on Self-Timed Clocking

Park, In-Cheol; Shin, MC; Kang , SH, IDEC Conference 2002 Summer, pp.119 - 122, 2002

4
Multi-thread VLIW processor architecture for HDTV decoding

Kim, H; Yang, WS; Shin, MC; Min, SJ; Bae, SO; Park, In-Cheol, CICC 2000: 22nd Annual Custom Integrated Circuits Conference, pp.559 - 562, CICC, 2000-05-21

5
Optimal down-conversion in compressed DCT domain with minimal operations

Shin, MC; Park, In-Cheol, Visual Communications and Image Processing 2000, pp.1613 - 1620, SPIE, 2000-06-20

6
Programmable Turbo Decoder Supporting Multiple Third-Generation Wireless Standards

박인철; Shin, MC, SOC Design Conference, 2002-10

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