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A 6b 28GS/s Four-channel Time-interleaved Current-Steering DAC with Background Clock Phase Calibration

Kim, WooCheol; Jo, Dong Shin; Roh, Yi-Ju; Kim, Ye Dam; Ryu, Seung-Tak, 39th Symposium on VLSI Technology / 33rd Symposium on VLSI Circuits, pp.C138 - C139, IEEE, 2019-06-11

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