Browse "EE-Conference Papers(학술회의논문)" by Author Park, In-Cheol
Showing results 1 to 60 of 171
| 6.4Gb/s multi-threaded BCH encoder and decoder for multi-channel SSD controllers Lee, Youngjoo; Yoo, Hoyoung; Yoo, Injae; Park, In-Cheol, 59th International Solid-State Circuits Conference, ISSCC 2012, pp.426 - 427, IEEE, 2012-02-22 |
| 6.4Gbps Multi-Threaded BCH Encoder and Decoder for Multi-Channel SSD Controllers Lee, Youngjoo; Yoo, Hoyoung; Yoo, Injae; Park, In-Cheol, IEEE International Solid-State Circuits Conference 2012 (ISSCC 2012), pp.426 - 427, IEEE, 2012-02-20 |
| 7.3 Gb/s Universal BCH Encoder and Decoder for SSD Controllers Yoo, Hoyoung; Lee, Youngjoo; Park, In-Cheol, 19th Asia and South Pacific Design Automation Conference, IEEE, 2014-01-21 |
| 8-Pipeline-Stage 32-bit Embedded Processor Using Dual Clock Domain Song, Jinook; Lee, Youngjoo; Kim, Bongjin; Park, In-Cheol, IEEE International SoC Design Conference (ISOCC 2011) Chip Design Contest, IEEE, 2011-11-17 |
| A 120-mW 0.16-ms-Latency Connectivity-Scalable Multiuser Detector for Interleave Division Multiple Access Kong, Byeong Yong; Park, In-Cheol, IEEE International Symposium on Circuits and Systems (ISCAS), pp.470 - 474, IEEE, 2020-10 |
| A 2.4pJ/bit, 6.37Gb/s SPC-enhanced BC-BCH decoder in 65nm CMOS for NAND flash storage systems Jung, Jaehwan; Park, In-Cheol; Lee, Youngjoo, 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), pp.329 - 330, IEEE, 2018-01 |
| A 2.6Gb/s 1.56mm2 near-optimal MIMO detector in 0.18um CMOS Kim, T.-H.; Park, In-Cheol, 32nd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2010, pp.1 - 4, CICC 2010, 2010-09-19 |
| A 2048-Point FFT Processor Based on Twiddle Factor Table Reduction Kim , JH; Park, In-Cheol, IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips 2007), pp.351 - 364, IEEE, 2007-04 |
| A 210mW graphics LSI implementing full 3D pipeline with 264Mtexels/s texturing for mobile multimedia applications Woo, R.; Cho,i S.; Sohn, J.-H.; Song, S.-J.; Bae, Y.-D.; Yoon, C.-W.; Nam, B.-G.; et al, 2003 Digest of Technical Papers, 2003-02-09 |
| A 24-bit floating-point audio DSP controller supporting fast exponentiation Lee, S.-W.; Kang, H.-J.; Park, In-Cheol, Proceedings of the 2003 IEEE International Symposium on Circuits and Systems, IEEE, 2003-05-25 |
| A 3Gb/s 2.08mm2 100b error-correcting BCH decoder in 0.13μm CMOS process Lee, Youngjoo; Yoo, Hoyoung; Park, In-Cheol, 18th Asia and South Pacific Design Automation Conference(ASP-DAC 2013), pp.85 - 86, IEEE, 2013-01-23 |
| A 4.75GOPS single-chip programmable processor array consisting of a multithreaded processor and multiple SIMD and IO processors Bae, Y.-D.; Park, In-Cheol, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, CICC, pp.583 - 586, 2004-10-03 |
| A 5-GHZ self-calibrated I/Q clock generator using a quadrature LC-VCO Ahn, H.K.; Park, In-Cheol; Kim, B., Proceedings of the 2003 IEEE International Symposium on Circuits and Systems, pp.797 - 800, IEEE, 2003-05-25 |
| A 50mbps double-binary turbo decoder for wiMAX based on bit-level extrinsic information exchange Kim, J.-H.; Park, In-Cheol, 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008, pp.305 - 308, IEEE, 2008-11-03 |
| A 6Gbps SSD Controller using Low-complexity and Time-interleaved BCH Encoder/Decoder Lee, Youngjoo; Yoo, Hoyoung; Yoo, Injae; Park, In-Cheol, IEEE International SoC Design Conference (ISOCC 2011) Chip Design Contest, IEEE, 2011-11-17 |
| A 80/20MHz 160mW multimedia processor integrated with embedded DRAM MPEG-4 accelerator and 3D rendering engine for mobile applications Yoon, C.-W.; Woo, R.; Kook, J.; Lee, S.-J.; Lee, K.; Bae, Y.-D.; Park, In-Cheol; et al, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, pp.142 - 143441, 2001-02-05 |
| A 870MHz 0.09mm2 0.45mW/MHz 32b embedded processor using 65nm CMOS technology Lee, Youngjoo; Kim, Bongjin; Park, In-Cheol, IEEE International SoC Design Conference (ISOCC 2012) Chip Design Contest, IEEE, 2012-11-05 |
| A Compiled-code Simulator with Reduced Edge Evaluation Yang, W.S.; Park, In-Cheol; Kyung, Chong-Min, APCHDL'98, pp.107 - 110, 1998-07 |
| A Fast Reed-Solomon Product-Code Decoder Without Redundant Computations Park, In-Cheol; Lee, HY, 2003 SoC Design Conference(SDC), pp.829 - 832, 2003-11-05 |
| A fast Reed-Solomon product-code decoder without redundant computations Lee, H.-Y.; Park, In-Cheol, 2004 IEEE International Symposium on Cirquits and Systems - Proceedings, IEEE, 2004-05-23 |
| A Fast Sine/Cosine Generator with Pipelined CORDIC and Table Lookup Method Shin, M.C.; Park, B.I.; Park, In-Cheol; Kyung, Chong-Min, '98 ASIC ON PROCEEDINGS, pp.281 - 284, 1998-10 |
| A Fixed-Point MPEG Audio Processor for Low Frequency Operation Yi, YS; Park, In-Cheol, International Symposium on Circuits and Systems (ISCAS), pp.300 - 303, 2002-05-26 |
| A Graph Matching Algorithm for Circuit Partitioning and Placement in Rectilinear Region and Nonplanar Surface Park, In-Cheol; Kyung, Chong-Min, Joint Technical Conference on Circuits/Systems, Computers and Communications, pp.182 - 186, 대한전자공학회, 1988 |
| A Hardware Accelerator for Phong Illumination Model in 3-Dimentional Grahpics Kwon, Y.S.; Park, In-Cheol; Kyung, Chong-Min, HUMANTECH, pp.277 - 285, 1999 |
| A Hardware Accelerator for the Specular Intensity of Phong Illumination Model in 3-Dimensional Kwon, Y. S.; Park, In-Cheol; Kyung, Chong-Min, ASP-DAC'2000, pp.559 - 564, 2000-01 |
| A High-Speed and Low-Latency Reed-solomon Decoder Based on a Dual-Line Structure Kang, HJ; Park, In-Cheol, International Conference on Acoustics, Speech, and Signal Processing (ICASSP), pp.3180 - 3183, 2002-05-13 |
| A hybrid delta-sigma modulator with adaptive calibration Shim, J.H.; Park, In-Cheol; Kim, B., Proceedings of the 2003 IEEE International Symposium on Circuits and Systems, IEEE, 2003-05-25 |
| A Low-Latency Multi-Touch Detector Based on Concurrent Processing of Redesigned Overlap Split and Connected Component Analysis Kong, Byeong Yong; Lee, Jooseung; Park, In-Cheol, IEEE International Symposium on Circuits and Systems, ISCAS 2020, Institute of Electrical and Electronics Engineers, 2020-10 |
| A low-power variable length decoder based on successive decoding of shoft codewords Lee, S.-W.; Park, In-Cheol, The 2001 International Symphosium on Circuits and Systems, pp.582 - 585, ISCAS, 2001-05-08 |
| A Low-Power Variable Length Decoder Based on Successive Decoding of Short Codewords Lee, SW; Park, In-Cheol, CAD 및 VLSI 설계연구회 학술발표대회, pp.157 - 162, 대한전자공학회, 2000-05 |
| A LOW-POWERr VARIABLE LENGHT DECODER BASED ON SUCCESSIVE DECODING OF SHOFT CODEWORDS Lee, SW; Park, In-Cheol, International Symphosium on Circuits and Systems(ISCS), pp.582 - 585, IEEE, 2001-05 |
| A Multi-Threading MPEG Processor with Variable Issue Modes Yang, W.S.; Kim, H.S.; Park, In-Cheol; Shin, M.C.; Kyung, Chong-Min, International Conference on VLSI and CAD(ICVC'99), pp.545 - 548, 1999-10 |
| A New Single-Clock Flip-Flop for Half-Swing Clocking Kwon, Y.S.; Park, B.I.; Park, In-Cheol; Kyung, Chong-Min, ASP-DAC'99, pp.117 - 120, ASP-DAC, 1999-01 |
| A novel trace-pipelined binary arithmetic coder architecture for JPEG2000 Rhu, M.; Park, In-Cheol, 2009 IEEE Workshop on Signal Processing Systems, SiPS 2009, pp.243 - 248, 2009-10-07 |
| A programmable turbo decoder for multiple 3G wireless standards Shin, M.-C.; Park, In-Cheol, IEEE International Solid-State Circuits Conference(ISSCC 2003), 2003-02-09 |
| A Programmable Turbo Decoder for Multiple Third-Generation Wireless Standards Park, In-Cheol; Shin, MC, International Solid-State Circuits Conference, ISCC, 2003-02-13 |
| A Regular Layout Structured Multiplier Based on Weighted Carry-Save Adders Park, B.I.; Park, In-Cheol; Kyung, Chong-Min, ICCD'99(International Conference on Computer Design), pp.243 - 248, 1999-10 |
| A Reverse Caculation for Low Power MAX-Log-MAP Turbo Decoder Choi, HM; Park, In-Cheol, The 12th Korean Conference on Semiconductors, pp.27 - 28, 2005-02 |
| A scalable and programmable sound synthesizer Kim, T.-H.; Lee, Y.-J.; Park, In-Cheol, 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009, pp.1855 - 1858, IEEE, 2009-05-24 |
| A scalable SIMD digital signal processor for high quality multifunctional printer systems Kang, HJ; Choi, Y; Kim, K.; Park, In-Cheol; Kim, JW; Lee, EH; Gahang, GS, Proceedings of SPIE-IS and T Electronic Imaging - Color Imaging X: Processing, Hardcopy, and Applications, pp.448 - 456, International Society for Optical Engineering (SPIE), 2005-01-17 |
| A Search-less DEC BCH Decoder for Low-Complexity Fault-Tolerant Systems Yoo, Injae; Park, In-Cheol, 2014 IEEE Workshop on Signal Processing Systems, IEEE, 2014-10-20 |
| A single-chip programmable platform based on a multithreaded processor and configurable logic clusters Bae, Y.-D.; Park, S.-I.; Yi, Y.; Park, In-Cheol, 2002 IEEE International Solid-State Circuits Conference, v.1, pp.336 - 337, 2002-02-03 |
| A Single-chip Programmable Platform with a Multithreaded RISC and Configurable Logic Clusters(Accepted) Bae, Young-Don; Park, Seong-Il; Park, In-Cheol, International Solid-State Circuits Conference(ISSCC 2002), pp.336 - 337, IEEE, 2002-02-07 |
| A unified parallel radix-4 turbo decoder for Mobile WiMAX and 3GPP-LTE Kim, J.-H.; Park, In-Cheol, 2009 IEEE Custom Integrated Circuits Conference, CICC '09, pp.487 - 490, 2009-09-13 |
| ACCENT : A CISC-Type Configurable Processor Core Chang, Y.S.; Park, B.I.; Yang, W.S.; Oh, H.S.; Park, In-Cheol; Kyung, Chong-Min, '98 ASIC ON PROCEEDINGS, pp.195 - 198, 1998-10 |
| Adaptive Metric Calculation for Improving Detection Capability of MIMO Detectors Kong, ByeongYong; Park, In-Cheol, IEEE 77th Vehicular Technology Conference 2013 (VTC 2013 - Spring), pp.1 - 5, IEEE, 2013-06-04 |
| An Area-Efficient Iterative Modified-Booth Multiplier Based on Self-Timed Clocking Park, In-Cheol; Shin, MC; Kang , SH, IDEC Conference 2002 Summer, pp.119 - 122, 2002 |
| An area-efficient iterative modified-booth multiplier based on self-timed clocking Shin, M.-C.; Kang, S.-H.; Park, In-Cheol, IEEE International Conference on: Computer Design: VLSI in Computers and Processors (ICCD 2001), pp.511 - 512, IEEE, 2001-09-23 |
| An Efficient Approach to Functional Verification of Complex Processors Lee, S.J.; Won, N.R.; Cho, H.C.; Park, B.I.; Chang, Y.S.; Park, S.I.; Park, In-Cheol; et al, International Conference on Chip Technology, 1998-04 |
| An energy-optimized (37840, 34320) symmetric BC-BCH decoder for healthy mobile storages Hwang, Seokha; Jung, Jaehwan; Kim, Daesung; Ha, Jeongseok; Park, In-Cheol; Lee, Youngjoo, 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC), IEEE, 2017-11-07 |
| An O(n3logn)-heuristic for microcode bit optimization Hong, SK; Park, In-Cheol; Kyung, CM, 1990 IEEE International Conference on Computer-Aided Design - ICCAD-90, pp.180 - 183, 1990-11-11 |
| Architecture design of a high-performance dual-symbol binary arithmetic coder for JPEG2000 Rhu, M.; Park, In-Cheol, 2009 IEEE International Conference on Image Processing, ICIP 2009, pp.2665 - 2668, 2009-11-07 |
| Area and power efficient design of coarse time synchronizer and frequency offset estimator for fixed WiMAX systems Kim, T.-H.; Park, In-Cheol, 2008 Asia and South Pacific Design Automation Conference, ASP-DAC, pp.111 - 112, IEEE, 2008-03-21 |
| Area-Efficient Digital Baseband Module for Bluetooth Wireless Communications Park, In-Cheol; Shin, MCl; Park, SI; Lee, SW; Kang, SH, 한국반도체학술대회 (KCS), pp.441 - 442, 2002-02 |
| Area-efficient digital baseband module for Bluetooth wireless communications Shin, M.-C.; Park, S.-I.; Lee, S.-W.; Kang, S.-H.; Park, In-Cheol, 2002 IEEE International Symposium on Circuits and Systems, pp.729 - 732, IEEE, 2002-05-26 |
| Area-efficient memory-based architecture for FFT processing Moon, S.-C.; Park, In-Cheol, Proceedings of the 2003 IEEE International Symposium on Circuits and Systems, v.5, 2003-05-25 |
| Array address translation for SDRAM-based video processing applications Kim, H; Park, In-Cheol, Visual Communications and Image Processing 2000, pp.922 - 931, SPIE, 2000-06-20 |
| Automotive ECU Platform using Fault-Tolerant Embedded Processor Yoo, Injae; Kim, Bongjin; Kong, Byeong Yong; Yoon, Dong Joon; Park, In-Cheol, IEEE International SoC Design Conference (ISOCC 2012) Chip Design Contest, IEEE, 2012-11-05 |
| Bluetooth 기저대역 모듈을 위한 USB 인터페이스의 설계 Park , SI; Park, In-Cheol, 한국반도체학술대회 (KCS), pp.255 - 256, 2002-02 |
| C-based RTL design verification methodology for complex microprocessor Yim, JS; Hwang, YH; Park, CJ; Choi, H; Yang, WS; Oh, HS; Park, In-Cheol; et al, Proceedings of the 1997 34th Design Automation Conference, pp.83 - 88, 1997-06-09 |
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