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Showing results 1 to 5 of 5

1
A 2.6b/cycle-Architecture-Based 10b 1.7GS/s 15.4mW 4x-Time-Interleaved SAR ADC with a Multistep Hardware-Retirement Technique

Hong, Hyeok-Ki; Kang, HW; Jo, DS; Lee, DS; You, YS; Lee, YH; Park, HJ; et al, International Solid-State Circuits Conference (ISSCC), IEEE, 2015-02-25

2
A 21fJ/conv-step 9 ENOB 1.6GS/s 2x Time-Interleaved FATI SAR ADC with Background Offset and Timing-Skew Calibration in 45nm CMOS

Sung, BRS; Jo, DS; Jang, IH; Lee, DS; You, YS; Lee, YH; Park, HJ; et al, International Solid-State Circuits Conference (ISSCC), IEEE, 2015-02-25

3
A 6 bit 2 GS/s flash-assisted time-interleaved (FATI) SAR ADC with background offset calibration

Sung, BRS; Lee, CK; Kim, W; Kim, JI; Hong, HK; Oh, GG; Lee, CH; et al, 2013 IEEE Asian Solid-State Circuits Conference, pp.281 - 284, IEEE, 2013-11-13

4
A Low-Power Quadtree Fractal Image Decoder

Kim, Lee-Sup; Kim, CH; Park, HJ, European Solid-State Circuits Conference, pp.414 - 417, 1999

5
Synchronization between Brain and Humanoid Robot using functional MRI

Lee, D; Jang, C; Nam, S; 김대식; Park, HJ, SNU-KAIST-ETHZ-EPFL Joint Symposium on Biomedical Engineering for Biomedical Applications 2012, SNU-KAIST-ETHZ-EPFL Joint Symposium on Biomedical Engineering for Biomedical Applications 2012, 2012-04-17

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