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Showing results 1 to 6 of 6

1
Fast Priority Balancing Circuit Partitioning for Multiple FPGAs using Time-multiplexed, Multicasting Interconnection

Kyung, Chong-Min; Kwon, Young-Su, 2003 SoC Design Conference(SDC), pp.412 - 416, 2003

2
FGA : Geometry Acceleration System with VLIW Processor in 3D Graphics

Kyung, Chong-Min; Kwon, Young-Su; Lee, Jun-Hee; Im, Yeon-Ho; Byun, Sung-Jae; Jeon, Young-Wook; Nam, Sang-Joon; et al, COOL Chips III, pp.261 - 270, 2000-04

3
FLOVA: a four-issue VLIW geometry processor with SIMD instructions and lighting acceleration unit

Nam, Sang-Joon; Kim, Byoung-Woon; Im, Yeon-Ho; Kwon, Young-Su; Lee, Jun-Hee; Cheon, Young-Wook; Byun, Sung-Jae; et al, CICC 2000: 22nd Annual Custom Integrated Circuits Conference, pp.551 - 554, CICC, 2000-05-21

4
Performance-Driven Event-Based Design Mapping in Multi-FPGA Simulation Accelerator

Kyung, Chong-Min; Kwon, Young-Su; Lee, Jae-Gon, International SoC Design Conference(ISOCC) 2004, pp.218 - 221, 2004-10

5
Signal Scheduling Driven Circuit Partitioning for Multiple FPGAs with Time-multiplexed Interconnection

Kyung, Chong-Min; Kwon, Young-Su; Yang, Woo-Seung, IFIP International Conference on Very Large Scale Integration(IFIP VLSI-SOC 2003), pp.123 - 128, 2003-12

6
Simulation Acceleration of Transaction-Level Models for SoC with RTL sub-blocks

Kyung, Chong-Min; Lee, Jae-Gon; Yang, Wooseung; Kwon, Young-Su; Kim, Young-Il, ASP-DAC'2005, 2005

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