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Showing results 1 to 6 of 6

1
Cost-effective TSV Redundancy Configuration

Jung, Jongpil; Kyung, Chong-Min; Yoon, Youngjun; Lee, Jae-Jin; Kang, Kyungsu, IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), pp.263 - 266, IEEE Computer Society, 2012-10-08

2
Exploring hybrid SRAM/MRAM L2 NUCA stacked on 3D chip-multiprocessors

Lee, Seunghan; Kang, Kyungsu; Jung, Jongpil; Kyung, Chong-Min, 11th International SoC Design Conference, ISOCC 2014, pp.26 - 27, Institute of Electrical and Electronics Engineers Inc., 2014-11

3
Integration of cache data allocation and voltage/frequency scaling for temperature-constrained multi-core systems with 3-D stacked cache memory

Kyung, Chong-Min; Kang, Kyungsu; Jung, Jongpil; Yoo, Sungjoo, The 54th International Midwest Symposium on Circuits and Systems (MWSCAS), 123, 2011-08-09

4
Runtime 3-D Stacked Cache Management for Chip-Multiprocessors

Jung, Jongpil; Kang, Kyungsu; Micheli, Giovanni De; Kyung, Chong-Min, International Symposium on Quality Electronic Design(ISQED), International Symposium on Quality Electronic Design(ISQED), 2013-03-05

5
Squeezing Maximizing Performance out of 3D Cache-Stacked Multicore Architectures

Kyung, Chong-Min; Khan, Asim; Kang, Kyungsu, The 54th International Midwest Symposium on Circuits and Systems (MWSCAS), 2011-08-08

6
Temperature-Aware Energy Minimization of 3D-Stacked L2 DRAM Cache through DVFS

Kyung, Chong-Min; Kang, Kyungsu; Jung, Jongpil; Yun, Woojin, International SoC Design Conference (ISOCC), IEEE, 2012-11-06

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