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Showing results 1 to 3 of 3

1
A 1,024-Channel, 64-Interconnect, Capacitive Neural Interface Using a Cross-Coupled Microelectrode Array and 2-Dimensional Code-Division Multiplexing

Choi, Woojun; Chen, Yiyang; Kim, Donghwan; Weaver, Sean; Schlotter, Tilman; Livanelioglu, Can; Liao, Jiawei; et al, 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023, Institute of Electrical and Electronics Engineers Inc., 2023-06-12

2
A Jitter-Programmable Bang-Bang Phase-Locked Loop using PVT Invariant Stochastic Jitter Monitor

Kim, Yong-Jo; Cho, SeongHwan; Jang, Taekwang, 2023 IEEE Asian Solid-State Circuits Conference, A-SSCC 2023, Institute of Electrical and Electronics Engineers Inc., 2023-11-08

3
An offset charge compensating biphasic neuro-stimulation for faradaic DC-current reduction

Cho, Donghyeok; Koo, Nahmil; Jang, Taekwang; Cho, SeongHwan, IEEE International Symposium on Circuits and Systems (IEEE ISCAS), Institute of Electrical and Electronics Engineers Inc., 2021-05

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